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authorRichard Spiegel <richard.spiegel@silverbackltd.com>2017-12-18 16:25:42 -0700
committerMartin Roth <martinroth@google.com>2018-02-02 20:51:17 +0000
commit9dc5600f860107f78b6da5d6717650587617b902 (patch)
tree3221634e43ca7c5dae2a38d0edc54e0b12d21410 /src/mainboard/google
parentadda3f810fd8202194b698d9fa06212a93ce81fb (diff)
mb/google/kahlee/mainboard.c: Create mainboard_pirq_data
When booting kahlee, there's an error message: "Warning: Can't write PCI IRQ assignments because 'mainboard_pirq_data' structure does not exist". This is generated by write_pci_cfg_irqs due to missing mainboard_pirq_data. BUG=b:70788755 TEST=Build and boot kahlee. Warning message must be gone. Change-Id: If07d2f54f06f6cf77566c43eddc8ee8a314e7a3a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/kahlee/mainboard.c26
1 files changed, 26 insertions, 0 deletions
diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c
index b080682b69..f1ae7b8d3e 100644
--- a/src/mainboard/google/kahlee/mainboard.c
+++ b/src/mainboard/google/kahlee/mainboard.c
@@ -22,6 +22,7 @@
#include <baseboard/variants.h>
#include <boardid.h>
#include <soc/nvs.h>
+#include <soc/pci_devs.h>
#include <soc/smi.h>
#include <soc/southbridge.h>
#include <variant/ec.h>
@@ -118,9 +119,34 @@ const u8 mainboard_intr_data[] = {
[0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
};
#endif
+
+/*
+ * This table defines the index into the picr/intr_data tables for each
+ * device. Any enabled device and slot that uses hardware interrupts should
+ * have an entry in this table to define its index into the FCH PCI_INTR
+ * register 0xC00/0xC01. This index will define the interrupt that it should
+ * use. Putting PIRQ_A into the PIN A index for a device will tell that
+ * device to use PIC IRQ 10 if it uses PIN A for its hardware INT.
+ */
+static const struct pirq_struct mainboard_pirq_data[] = {
+ { PCIE0_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } },
+ { PCIE1_DEVFN, { PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A } },
+ { PCIE2_DEVFN, { PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B } },
+ { PCIE3_DEVFN, { PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C } },
+ { PCIE4_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } },
+ { HDA0_DEVFN, { PIRQ_NC, PIRQ_HDA, PIRQ_NC, PIRQ_NC } },
+ { SD_DEVFN, { PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
+ { SMBUS_DEVFN, { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
+ { SATA_DEVFN, { PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
+ { EHCI1_DEVFN, { PIRQ_EHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
+ { XHCI_DEVFN, { PIRQ_XHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
+};
+
/* PIRQ Setup */
static void pirq_setup(void)
{
+ pirq_data_ptr = mainboard_pirq_data;
+ pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
intr_data_ptr = mainboard_intr_data;
picr_data_ptr = mainboard_picr_data;
}