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authorShelley Chen <shchen@google.com>2019-10-08 14:17:26 -0700
committerShelley Chen <shchen@google.com>2019-10-09 22:01:23 +0000
commit9b93383f5b7b7e27692a8a55ad2f666dd6f08c62 (patch)
tree9c01ba2b9b390d2865acc10732c5b98b1d546576 /src/mainboard/google
parent86b683a888e46faea087e9fedae11792cb5d273a (diff)
mb/google/hatch: Set FPS as wake source
BUG=b:142131099 BRANCH=None TEST=powerd_dbus_suspend, ensure DUT in S0ix touch fp sensor and ensure DUT wakes up in S0 Change-Id: If57094aa1076d79ac0886b71fa5532411bfeb45f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/hatch/variants/baseboard/gpio.c2
-rw-r--r--src/mainboard/google/hatch/variants/dratini/overridetree.cb3
-rw-r--r--src/mainboard/google/hatch/variants/hatch/overridetree.cb3
-rw-r--r--src/mainboard/google/hatch/variants/helios/overridetree.cb3
-rw-r--r--src/mainboard/google/hatch/variants/kohaku/overridetree.cb3
5 files changed, 9 insertions, 5 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c
index 240bb5d23b..f8df44775a 100644
--- a/src/mainboard/google/hatch/variants/baseboard/gpio.c
+++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c
@@ -59,7 +59,7 @@ static const struct pad_config gpio_table[] = {
/* A22 : FPMCU_PCH_BOOT0 */
PAD_CFG_GPO(GPP_A22, 0, DEEP),
/* A23 : FPMCU_PCH_INT_ODL */
- PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT),
+ PAD_CFG_GPI_IRQ_WAKE(GPP_A23, NONE, PLTRST, LEVEL, INVERT),
/* B0 : CORE_VID0 */
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb
index 65649d1d45..1af822d43f 100644
--- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb
@@ -140,7 +140,8 @@ chip soc/intel/cannonlake
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "uid" = "1"
register "compat_string" = ""google,cros-ec-spi""
- register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)"
+ register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)"
+ register "wake" = "GPE0_DW0_23"
device spi 1 on end
end # FPMCU
end # GSPI #1
diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb
index df2cc381e9..bc6aa11cab 100644
--- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb
@@ -171,7 +171,8 @@ chip soc/intel/cannonlake
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "uid" = "1"
register "compat_string" = ""google,cros-ec-spi""
- register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)"
+ register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)"
+ register "wake" = "GPE0_DW0_23"
device spi 1 on end
end # FPMCU
end # GSPI #1
diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb
index 8ca878d43c..0902340e56 100644
--- a/src/mainboard/google/hatch/variants/helios/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb
@@ -180,7 +180,8 @@ chip soc/intel/cannonlake
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "uid" = "1"
register "compat_string" = ""google,cros-ec-spi""
- register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)"
+ register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)"
+ register "wake" = "GPE0_DW0_23"
device spi 1 on end
end # FPMCU
end # GSPI #1
diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb
index 37914faa06..bd60973497 100644
--- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb
@@ -238,7 +238,8 @@ chip soc/intel/cannonlake
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "uid" = "1"
register "compat_string" = ""google,cros-ec-spi""
- register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)"
+ register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)"
+ register "wake" = "GPE0_DW0_23"
device spi 1 on end
end # FPMCU
end # GSPI #1