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authorSumeet Pawnikar <sumeet.r.pawnikar@intel.com>2016-12-22 13:53:16 +0530
committerMartin Roth <martinroth@google.com>2016-12-26 17:36:55 +0100
commit88766be48806a10d870e7a3e3fddbf7e6998056c (patch)
tree1e957ee85603f9523fa0f6f36ce22a2021ab0c50 /src/mainboard/google
parent9d2f3de48c3f9fbca0124b2f851e6057e2f43a1b (diff)
mainboard/google/chell: Set TCC activation offset to 10 degree C
With the default TCC activation offset value as 0 and Tjmax temperature value as 100 degree C, Pcode firmware starts taking prochot action at 100 degree C [Tjmax-Offset]. But before Pcode firmware starts prochot action at 100 degree C, device is getting shutdown at 99 degree C due to DPTF critical CPU temperature. This patch sets TCC activation offset value to 10 degree C for thermal throttle action to prevent this kind of shutdown. BUG=chrome-os-partner:59397 BRANCH=None. TEST=Built, booted on skylake and verified target offset value. Change-Id: I0811ef481a4b3ce4bd6ef24f2aa8160f44f9c990 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17921 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/chell/devicetree.cb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index 34250d3450..2ffaec6946 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -183,6 +183,8 @@ chip soc/intel/skylake
# PL2 override 15W
register "tdp_pl2_override" = "15"
+ register "tcc_offset" = "10" # TCC of 90C
+
# Send an extra VR mailbox command for the supported MPS IMVP8 model
register "SendVrMbxCmd" = "1"