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authorNick Vaccaro <nvaccaro@google.com>2020-05-21 10:54:55 -0700
committerNick Vaccaro <nvaccaro@google.com>2020-05-21 23:59:33 +0000
commit47b5a9820f2f95fda349f298054ca40cc2149548 (patch)
tree2c00a2bdea37563f1585ea182baf760d3a39becd /src/mainboard/google
parent105e02d4fd99dba55d603d010802eebdebeee535 (diff)
mb/google/volteer: set DRAM Max Cycle Time to 15
The DRAM Max Cycle Time (tCKmax) for Samsung's K4UBE3D4AA-MGCL DRAM part should be set to 0xF. BUG=b:157178553, b:156555863 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot a SKU4 volteer to the kernel and run "memtester 6G 100" and verify it completes successfully without error and does not crash. Change-Id: Id95b19fe261e3f57a52a43055acab99af66b14ab Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41634 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex b/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex
index 90202f983c..778967d5e7 100644
--- a/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex
+++ b/src/mainboard/google/volteer/variants/volteer/spd/SPD_LPDDR4X_200b_8bank_2Rx16_32Gb_DDP_4267.spd.hex
@@ -1,5 +1,5 @@
23 11 11 0E 15 21 B5 08 00 00 00 00 0A 01 00 00
-48 00 04 00 92 54 05 00 87 00 90 A8 90 C0 08 60
+48 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60
04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00