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authorFurquan Shaikh <furquan@google.com>2020-06-23 11:07:22 -0700
committerFurquan Shaikh <furquan@google.com>2020-07-01 17:54:34 +0000
commit1247616304ebf9a8839a6808be2f12912b1d98f8 (patch)
tree9870e15580b478b53c44d126f922b6cb2ff94ab8 /src/mainboard/google
parent17c46042eb9350a1cdc0d6cb68bcfa1850abd0fd (diff)
mb/google/zork: Reconfigure PCIE_RST1_L as GPO driven low on sleep path
This change configures PCIE_RST1_L as GPO driven low on the sleep path. This is required to keep PERST# asserted to devices until coreboot deasserts it on S3 resume path. Without this change, on S3 resume, PCIE_RST1_L gets deasserted sooner than required resulting in violation of PCIe reset timings. With this change, the behavior of PCIE_RST1_L is as follows: 1. GPIO27 is configured as NF (PCIE_RST1_L) in coreboot bootblock/romstage and driven high. 2. On S3 entry, GPIO27 is configured as GPO driven low. * Boot out of G3: Timing should be met since GPIO_27 is pulled down by default until coreboot configures it. * S3 resume: Timing should be met since GPIO_27 is configured as GPO low and it retains state across S3 entry/exit. So, should be low until coreboot configures it. * Warm reset: Timing should be met since it is configured as NF. So, hardware guarantees the reset timing as seen in "warm reset.jpg" in #46. BUG=b:152582706 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ia0ad1522edc438fd054d927ef4a2ab5c27329c00 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2261116 Reviewed-by: Aaron Durbin <adurbin@google.com> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
index e43b0b4cff..1dd2dd5b89 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_common.c
@@ -34,6 +34,8 @@ const __weak struct soc_amd_gpio *variant_early_gpio_table(size_t *size)
static const struct soc_amd_gpio gpio_sleep_table[] = {
/* PEN_POWER_EN */
PAD_GPO(GPIO_5, LOW),
+ /* PCIE_RST1_L */
+ PAD_GPO(GPIO_27, LOW),
/* EN_PWR_CAMERA */
PAD_GPO(GPIO_76, LOW),
};