soc/amd: commonize generation of the PIC/APIC mapping tables

Now that we have a common init_tables in all mainboards using AMD SoCs,
both the population of the fch_pic_routing and fch_apic_routing arrays
and the definition of those arrays can be moved to the common AMD SoC
code to not have the code duplicated in all mainboards.

BUG=b:182782749

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I8c65eca258272f0ef7dec3ece6236f5d00954c66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68853
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 3 insertions, 47 deletions

diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c
index aaa254893e..90c74d7e4e 100644
--- a/src/mainboard/google/zork/mainboard.c
+++ b/src/mainboard/google/zork/mainboard.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#include <string.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/mmio.h>
@@ -31,16 +30,8 @@
 #define METHOD_MAINBOARD_WAK       "\\_SB.MWAK"
 #define METHOD_MAINBOARD_PTS       "\\_SB.MPTS"
 
-/***********************************************************
- * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
- * This table is responsible for physically routing the PIC and
- * IOAPIC IRQs to the different PCI devices on the system.  It
- * is read and written via registers 0xC00/0xC01 as an
- * Index/Data pair.  These values are chipset and mainboard
- * dependent and should be updated accordingly.
- */
-static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES];
-static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES];
+/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
+   accessed via I/O ports 0xc00/0xc01. */
 
 /*
  * This controls the device -> IRQ routing.
@@ -78,42 +69,12 @@ static const struct fch_irq_routing fch_irq_map[] = {
 	{ PIRQ_MISC2,	0x00,		0x00 },
 };
 
-static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
+const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
 {
 	*length = ARRAY_SIZE(fch_irq_map);
 	return fch_irq_map;
 }
 
-static void init_tables(void)
-{
-	const struct fch_irq_routing *mb_irq_map;
-	size_t mb_fch_irq_mapping_table_size;
-	size_t i;
-
-	mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size);
-
-	memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing));
-	memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing));
-
-	for (i = 0; i < mb_fch_irq_mapping_table_size; i++) {
-		if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) {
-			printk(BIOS_WARNING,
-			       "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n",
-			       mb_irq_map[i].intr_index, i);
-			continue;
-		}
-		fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num;
-		fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num;
-	}
-}
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
-	intr_data_ptr = fch_apic_routing;
-	picr_data_ptr = fch_pic_routing;
-}
-
 static void mainboard_configure_gpios(void)
 {
 	size_t base_num_gpios, override_num_gpios;
@@ -205,12 +166,7 @@ static void mainboard_fill_ssdt(const struct device *dev)
  *************************************************/
 static void mainboard_enable(struct device *dev)
 {
-	init_tables();
-	/* Initialize the PIRQ data structures for consumption */
-	pirq_setup();
-
 	dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
-
 }
 
 static void mainboard_final(void *chip_info)