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authorFelix Held <felix-coreboot@felixheld.de>2021-06-15 20:09:40 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-06-16 19:16:44 +0000
commitaa7eb08dc869982b20fda48cabe8066ede0e92f0 (patch)
treeffa1ac31b3bed95851c5cb24a819bd7c142edec0 /src/mainboard/google/zork
parent97fc054979d709bd84861e046b451cf2abc97fbc (diff)
mb/google/zork: enable UART0 in devicetree
This a mainly a preparation for adding the MMIO UART devices to the chipset devicetree. TEST=none Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I533e4a909fdeb1614dbc5df015440b9df5d83233 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/mainboard/google/zork')
-rw-r--r--src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb1
-rw-r--r--src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb1
2 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
index aa70616a94..f17eca77ca 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
@@ -395,6 +395,7 @@ chip soc/amd/picasso
end
end
+ device mmio 0xfedc9000 on end # console on UART0
device mmio 0xfedca000 off end # UART1
device mmio 0xfedce000 off end # UART2
device mmio 0xfedcf000 off end # UART3
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
index 3bf6fbc429..88fa360743 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb
@@ -437,6 +437,7 @@ chip soc/amd/picasso
end
end
+ device mmio 0xfedc9000 on end # console on UART0
device mmio 0xfedca000 off end # UART1
device mmio 0xfedce000 off end # UART2
device mmio 0xfedcf000 off end # UART3