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authorKevin Chiu <kevin.chiu.17802@gmail.com>2021-02-09 12:05:29 +0800
committerMartin Roth <martinroth@google.com>2021-02-10 16:21:00 +0000
commit1deca23f0aae91c49bb828dbea8b0a268c7c88ef (patch)
tree4c881dfe8f6c79b6adb147863ea56a3bdd2337b6 /src/mainboard/google/zork
parent6dd2e7b9268a8accf058ca3d4230762d24c17c6e (diff)
mb/google/zork: modify ELAN TS i2c IRQ to LEVEL active for dirinboz
EDGE IRQ from TS might be invalid to HOST, configure IRQs as level triggered to prevent TS lost. BUG=b:179594439 BRANCH=zork TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on, suspend DUT to check TS is functional Change-Id: Ibbbc73b37932ba1359ffe6f572a15564bb341025 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50416 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/zork')
-rw-r--r--src/mainboard/google/zork/variants/dirinboz/overridetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb
index 1bfea1d1c4..283b1fc0e3 100644
--- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb
+++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb
@@ -120,7 +120,7 @@ chip soc/amd/picasso
register "hid" = ""ELAN0001""
register "desc" = ""ELAN Touchscreen""
register "probed" = "1"
- register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)"
+ register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)"
register "enable_delay_ms" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)"