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authorFurquan Shaikh <furquan@google.com>2020-06-29 13:39:21 -0700
committerFurquan Shaikh <furquan@google.com>2020-06-30 23:31:01 +0000
commit10185866f08a192d6fddb6f707d6877fcd81cb94 (patch)
treeadc8accaf5f1e1495d7ef0eb899032af95ca2d25 /src/mainboard/google/zork
parent05726e8e699e4874ef4290cd07e0cdb2590d4fe1 (diff)
soc/amd/gpio, mb/{amd,google}: Configure pads using a single entry in GPIO configuration table
Currently, for Stoneyridge and Picasso mainboards, pads that are configured for SCI/SMI/WAKE need to have multiple entries in the configuration table - one for PAD_GPI and other for the special configuration that is required. This requires a very specific ordering of pads within the table and is prone to errors because of conflicting params provided to the different entries for the same pad. This also does not work very well with the concept of override GPIOs where the entry in base table is overridden with the first matched entry from the override table. This change updates the way GPIO configuration is handled for special routing like SCI/SMI/WAKE/DEBOUNCE by setting the control field of soc_amd_gpio structure in the macros performing these configurations. Also, program_gpios() is updated to perform a write to GPIO control register instead of read-modify-write. This is because mainboard is expected to provide only a single configuration entry for each pad within a given table. Thus, there is no need to preserve earlier configuration. Mainboards that were providing multiple entries for a single pad are updated accordingly. BUG=b:159944426 Change-Id: I3364dc2982d66c4e33c2b4e6b0b97641ebea27f0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42875 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/zork')
-rw-r--r--src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c2
-rw-r--r--src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c3
2 files changed, 0 insertions, 5 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
index ba50362685..5874e89c06 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
@@ -13,7 +13,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = {
/* PEN_POWER_EN - reset */
PAD_GPO(GPIO_5, LOW),
/* EC_FCH_WAKE_L */
- PAD_GPI(GPIO_24, PULL_UP),
PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
/* PCIE_RST1_L - Variable timings (May remove) */
PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
@@ -47,7 +46,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom_v3[] = {
/* EN_PWR_TOUCHPAD_PS2 - reset */
PAD_GPO(GPIO_6, LOW),
/* EC_FCH_WAKE_L */
- PAD_GPI(GPIO_24, PULL_UP),
PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
/* PCIE_RST1_L - Variable timings (May remove) */
PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
index 01aef2bb11..21917939ae 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
@@ -13,7 +13,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom_pre_v3[] = {
/* PEN_POWER_EN - reset */
PAD_GPO(GPIO_5, LOW),
/* EC_FCH_WAKE_L */
- PAD_GPI(GPIO_24, PULL_UP),
PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
/* PCIE_RST1_L - Variable timings (May remove) */
PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
@@ -45,7 +44,6 @@ static const struct soc_amd_gpio gpio_set_stage_rom_v3[] = {
/* EN_PWR_TOUCHPAD_PS2 - reset */
PAD_GPO(GPIO_13, LOW),
/* EC_FCH_WAKE_L */
- PAD_GPI(GPIO_24, PULL_UP),
PAD_WAKE(GPIO_24, PULL_UP, EDGE_LOW, S3_S4_S5),
/* PCIE_RST1_L - Variable timings (May remove) */
PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
@@ -82,7 +80,6 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
/* PEN_POWER_EN - Enabled*/
PAD_GPO(GPIO_5, HIGH),
/* FPMCU_INT_L */
- PAD_GPI(GPIO_6, PULL_UP),
PAD_WAKE(GPIO_6, PULL_UP, EDGE_LOW, S3_S4_S5),
/* I2S_SDIN */
PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE),