diff options
| author | Kevin Chiu <Kevin.Chiu@quantatw.com> | 2020-11-03 15:28:22 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-11-22 17:36:25 +0000 |
| commit | d029a579badd2e71e87b84f66e5fbe87c1651bee (patch) | |
| tree | 19b6b43a43cc4a4efbb9418726f9b11d5d77a3bf /src/mainboard/google/zork | |
| parent | 9065f4f8ed2facb60df3f4906b8e1e66e8958379 (diff) | |
mb/google/zork: update berknip CHTC thermal setting
Update APU CHTC thermal temperature protection point:
Temperature limit(C'): 90
Update system config=2 to meet TDP 15W design.
BUG=b:162377903
BRANCH=zork
TEST=1. emerge-zork coreboot
2. check CHTC temperature by AMD utility
Change-Id: I03245a824d838c2d9468ae0fa3cfa34389560e9d
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/google/zork')
| -rw-r--r-- | src/mainboard/google/zork/variants/berknip/overridetree.cb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb index 602b5c79de..f563419b29 100644 --- a/src/mainboard/google/zork/variants/berknip/overridetree.cb +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -6,7 +6,7 @@ chip soc/amd/picasso # For the below fields, 0 indicates use SOC default # System config index - register "system_config" = "3" + register "system_config" = "2" # Set STAPM confiuration. All of these fields must be set >0 to take affect register "slow_ppt_limit_mW" = "20000" @@ -14,6 +14,7 @@ chip soc/amd/picasso register "slow_ppt_time_constant_s" = "5" register "stapm_time_constant_s" = "200" register "sustained_power_limit_mW" = "12000" + register "thermctl_limit_degreeC" = "90" register "telemetry_vddcr_vdd_slope_mA" = "65599" register "telemetry_vddcr_vdd_offset" = "0" |