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authorRaul E Rangel <rrangel@chromium.org>2020-09-29 14:20:48 -0600
committerPaul Fagerburg <pfagerburg@chromium.org>2020-10-08 22:23:42 +0000
commitcada76333f4d703707d325d65756026bbf5db115 (patch)
tree74a3701d90f7758a7f893901bf7fa16cd04bb2b5 /src/mainboard/google/zork
parent481ab24f46fc3e15b501d0aeb0e494b9cbd390d6 (diff)
mb/google/zork/ezkinil: Increase eMMC initial clock frequency
This will reduce boot time by 7ms. Some of the initial designs don't have a pull-up resistor on the CMD line. These designs still boot at 400 kHz despite not having the pull-up. BUG=b:158766134 TEST=Boot Ezkinil w/ eMMC to OS. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ida0bbf9bd772ab7d384d5d097fa3b02b846a3efa Reviewed-on: https://review.coreboot.org/c/coreboot/+/45852 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/zork')
-rw-r--r--src/mainboard/google/zork/variants/ezkinil/overridetree.cb6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb
index 26af3942a8..5ef2f0ac77 100644
--- a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb
+++ b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb
@@ -44,6 +44,12 @@ chip soc/amd/picasso
.early_init = true,
}"
+ register "emmc_config" = "{
+ .timing = SD_EMMC_EMMC_HS400,
+ .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A,
+ .init_khz_preset = 400,
+ }"
+
# See AMD 55570-B1 Table 13: PCI Device ID Assignments.
device domain 0 on
subsystemid 0x1022 0x1510 inherit