diff options
| author | Chris Wang <chris.wang@amd.corp-partner.google.com> | 2021-03-02 22:33:00 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-03-10 23:03:59 +0000 |
| commit | 216d69d459ba685c2aeb42b00c1cef7be2482864 (patch) | |
| tree | 79ed3d1552be87429cf42af59043abf430cd9124 /src/mainboard/google/zork | |
| parent | 9a6bc07cc26a93c434bc8dac86cf13c0edef09a8 (diff) | |
mb/google/zork: add UPDM updating function before runing FSP-M
Add the UPD updating hook in early stage for customization.
BUG=b:117719313
BRANCH=zork
TEST=build,check the hook function been executed.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I4954a438a51b29b086015624127e651fd06f971b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51181
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/zork')
| -rw-r--r-- | src/mainboard/google/zork/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/mainboard/google/zork/romstage.c | 11 | ||||
| -rw-r--r-- | src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h | 3 |
3 files changed, 15 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/Makefile.inc b/src/mainboard/google/zork/Makefile.inc index 8a9d7af89a..4aac8f4884 100644 --- a/src/mainboard/google/zork/Makefile.inc +++ b/src/mainboard/google/zork/Makefile.inc @@ -4,6 +4,7 @@ bootblock-y += bootblock.c romstage-y += chromeos.c romstage-y += sku_id.c +romstage-y += romstage.c ramstage-y += chromeos.c ramstage-y += ec.c diff --git a/src/mainboard/google/zork/romstage.c b/src/mainboard/google/zork/romstage.c new file mode 100644 index 0000000000..9ad167768f --- /dev/null +++ b/src/mainboard/google/zork/romstage.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <soc/romstage.h> + +void __weak variant_updm_update(FSP_M_CONFIG *mcfg) {} + +void mainboard_updm_update(FSP_M_CONFIG *mcfg) +{ + variant_updm_update(mcfg); +} diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index ac600de255..230f059972 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -6,6 +6,7 @@ #include <stddef.h> #include <boardid.h> #include <ec/google/chromeec/ec.h> +#include <FspmUpd.h> #include <soc/platform_descriptors.h> #include "chip.h" @@ -32,6 +33,8 @@ const struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int slp_ty */ const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ); +void variant_updm_update(FSP_M_CONFIG *mcfg); + /* Program any required GPIOs at the finalize phase */ void finalize_gpios(int slp_typ); /* Modify devictree settings during ramstage. */ |