mb/google/zork: Init fingerprint GPIOs for boot vs resume

Add a function that initializes GPIOs based on the sleep type that
the system is coming back from.  This allows initialization of the
fingerprint GPIOs which need to be handled differently between wake
from S3 and boot from S5.

On initial boot, the state of the FP sensor could be either
enabled or disabled.  Because of this, on boot, we power off
the sensor for >200ms, to reset its state, then power it back on.

In suspend/resume, the fingerprint sensor should remain powered
the entire time.

If fingerprint is disabled on the trembyle-based board, set the pins
to no-connect.  Dalboz doesn't have fingerprint and the GPIOS are
configured differently due to the FT5 chip having fewer GPIOS than
FP5, so nothing needs to be initialized there.

There were also a couple of trivial comment clean ups regarding the
FPMCU GPIOS.

BUG=b:171837716
TEST=Boot & Check GPIO states.
BRANCH=Zork

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I16a2e621145782e0a908bb3e49478586c09a0e0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

1 files changed, 28 insertions, 0 deletions

diff --git a/src/mainboard/google/zork/variants/baseboard/helpers.c b/src/mainboard/google/zork/variants/baseboard/helpers.c
index 70710351d2..d12a8ed407 100644
--- a/src/mainboard/google/zork/variants/baseboard/helpers.c
+++ b/src/mainboard/google/zork/variants/baseboard/helpers.c
@@ -149,3 +149,31 @@ int variant_get_daughterboard_id(void)
 {
 	return extract_field(FW_CONFIG_MASK_DB_INDEX, FW_CONFIG_DB_INDEX_SHIFT);
 }
+
+bool variant_has_fingerprint(void)
+{
+	if (CONFIG(VARIANT_HAS_FPMCU))
+		return true;
+
+	return false;
+}
+
+bool fpmcu_needs_delay(void)
+{
+	/*
+	 *  Older board versions need an extra delay here to finish resetting
+	 *  the FPMCU.  The resistor value in the glitch prevention circuit was
+	 *  sized so that the FPMCU doesn't turn of for ~1 second.  On newer
+	 *  boards, that's been updated to ~30ms, which allows the FPMCU's
+	 *  reset to be completed in the time between bootblock and finalize.
+	 */
+	uint32_t board_version;
+
+	if (google_chromeec_cbi_get_board_version(&board_version))
+		board_version = 1;
+
+	if (board_version <= CONFIG_VARIANT_MAX_BOARD_ID_BROKEN_FMPCU_POWER)
+		return true;
+
+	return false;
+}