diff options
author | Furquan Shaikh <furquan@google.com> | 2020-06-29 11:56:04 -0700 |
---|---|---|
committer | Furquan Shaikh <furquan@google.com> | 2020-07-01 17:55:19 +0000 |
commit | 70b7fa1434d63529db3a433c3bd62ccab54611d7 (patch) | |
tree | f9c9bdf07be55dfb66ecee9b3aa1606975487167 /src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c | |
parent | 189a5c7cf6cee32e823dc4c2589ff566703a8cfd (diff) |
mb/google/zork: Add support for active low wifi power enable
A late change went into v3+ of reference schematics which inverted
EN_PWR_WIFI to meet PCIe reset/power timings for WiFi device. This is
incorporated into v3.51+ for Trembyle reference and v3.2+ for Dalboz
reference. However, some variants are built with v3+ reference
schematics, but without the inversion of EN_PWR_WIFI polarity. Thus,
we need to add support for following combinations:
1. Pre-v3 Schematics
2. V3+ Schematics
3. V3+ Schematics + Active low wifi power
This change adds a new Kconfig
`VARIANT_MIN_BOARD_ID_WIFI_POWER_ACTIVE_LOW` that sets the minimum
board ID that has EN_PWR_WIFI active low in hardware. Variants that
missed this change in V3+ integration (berknip and vilboz) have board
IDs set to VARIANT_MIN_BOARD_ID_V3_SCHEMATICS + 1. For others, this
defaults to VARIANT_MIN_BOARD_ID_V3_SCHEMATICS.
BUG=b:159749536
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib8da7fba5f4a518a51b203d6a01a9551e261d8b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c')
-rw-r--r-- | src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c | 43 |
1 files changed, 39 insertions, 4 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index c9ad96bfde..835cf9964f 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -211,27 +211,62 @@ const __weak struct sci_source *get_gpe_table(size_t *num) return NULL; } -static void wifi_power_reset_configure_v3(void) +static void wifi_power_reset_configure_active_low_power(void) { /* * Configure WiFi GPIOs such that: * - WIFI_AUX_RESET_L is configured first to assert PERST# to WiFi device. - * - Enable power to WiFi using EN_PWR_WIFI. + * - Enable power to WiFi using EN_PWR_WIFI_L. * - Wait for 50ms after power to WiFi is enabled. * - Deassert WIFI_AUX_RESET_L. */ static const struct soc_amd_gpio v3_wifi_table[] = { /* WIFI_AUX_RESET_L */ PAD_GPO(GPIO_86, LOW), + /* EN_PWR_WIFI_L */ + PAD_GPO(GPIO_42, LOW), + }; + program_gpios(v3_wifi_table, ARRAY_SIZE(v3_wifi_table)); + + mdelay(50); + gpio_set(GPIO_86, 1); +} + +static void wifi_power_reset_configure_active_high_power(void) +{ + /* + * When GPIO_42 is configured as active high for enabling WiFi power, WIFI_AUX_RESET_L + * gets pulled high because of external PU to PP3300_WIFI. Thus, EN_PWR_WIFI needs to be + * set low before driving it high to trigger a WiFi power cycle to meet PCIe + * requirements. Thus, configura GPIOs such that: + * - WIFI_AUX_RESET_L is configured first to assert PERST# to WiFi device + * - Disable power to WiFi. + * - Wait 10ms for WiFi power to go low. + * - Enable power to WiFi using EN_PWR_WIFI. + * - Deassert WIFI_AUX_RESET_L. + */ + static const struct soc_amd_gpio v3_wifi_table[] = { + /* WIFI_AUX_RESET_L */ + PAD_GPO(GPIO_86, LOW), /* EN_PWR_WIFI */ - PAD_GPO(GPIO_42, HIGH), + PAD_GPO(GPIO_42, LOW), }; program_gpios(v3_wifi_table, ARRAY_SIZE(v3_wifi_table)); + mdelay(10); + gpio_set(GPIO_42, 1); mdelay(50); gpio_set(GPIO_86, 1); } +static void wifi_power_reset_configure_v3(uint32_t board_version) +{ + if (board_version >= CONFIG_VARIANT_MIN_BOARD_ID_WIFI_POWER_ACTIVE_LOW) + wifi_power_reset_configure_active_low_power(); + else + wifi_power_reset_configure_active_high_power(); +} + static void wifi_power_reset_configure_pre_v3(void) { /* @@ -264,7 +299,7 @@ __weak void variant_pcie_power_reset_configure(void) if (!google_chromeec_cbi_get_board_version(&board_version) && (board_version >= CONFIG_VARIANT_MIN_BOARD_ID_V3_SCHEMATICS)) - wifi_power_reset_configure_v3(); + wifi_power_reset_configure_v3(board_version); else wifi_power_reset_configure_pre_v3(); } |