diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2020-07-29 13:54:22 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2020-07-30 20:05:55 +0000 |
| commit | 80e2dd88542581fe637b3ee7825bfe4c65811bba (patch) | |
| tree | bf091e007ec8db33b03f2da5b7245aad703959f3 /src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c | |
| parent | 821b1e2f28b875f353b30bcd6b286d3eeae85c7b (diff) | |
mb/google/zork: remove indirection for dxio lane configuration
There was a mix of open coding DXIO logical lane numbers and clkreq
pins. And there are separate macros depending on the baseboard
as well as processor type. Remove the indirection and supply the values
directly in the descriptors.
BUG=b:162423378
Change-Id: I779cb0a514e3b668265e6039d6e7e7bd0f3d49ed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c')
| -rw-r--r-- | src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c index 75c2211ee9..26a5d33a1b 100644 --- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c @@ -31,7 +31,7 @@ static const fsp_dxio_descriptor pco_dxio_descriptors[] = { .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = NVME_CLKREQ, + .clk_req = CLK_REQ4, }, { // WLAN @@ -45,7 +45,7 @@ static const fsp_dxio_descriptor pco_dxio_descriptors[] = { .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = WLAN_CLKREQ, + .clk_req = CLK_REQ0, .clk_pm_support = true, }, { @@ -60,7 +60,7 @@ static const fsp_dxio_descriptor pco_dxio_descriptors[] = { .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = SD_CLKREQ, + .clk_req = CLK_REQ1, } }; @@ -69,45 +69,45 @@ static const fsp_dxio_descriptor dali_dxio_descriptors[] = { // NVME SSD .port_present = true, .engine_type = PCIE_ENGINE, - .start_logical_lane = NVME_START_LANE, - .end_logical_lane = NVME_END_LANE, + .start_logical_lane = 0, + .end_logical_lane = 1, .device_number = 1, .function_number = 7, .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = NVME_CLKREQ, + .clk_req = CLK_REQ4, .clk_pm_support = true, }, { // WLAN .port_present = true, .engine_type = PCIE_ENGINE, - .start_logical_lane = WLAN_START_LANE, - .end_logical_lane = WLAN_END_LANE, + .start_logical_lane = 4, + .end_logical_lane = 4, .device_number = 1, .function_number = 2, .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = WLAN_CLKREQ, + .clk_req = CLK_REQ0, .clk_pm_support = true, }, { // SD Reader .port_present = true, .engine_type = PCIE_ENGINE, - .start_logical_lane = SD_START_LANE, - .end_logical_lane = SD_END_LANE, + .start_logical_lane = 5, + .end_logical_lane = 5, .device_number = 1, .function_number = 3, .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = SD_CLKREQ, + .clk_req = CLK_REQ1, } }; |