diff options
author | Bob Moragues <moragues@google.com> | 2018-11-26 14:40:46 -0800 |
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committer | Duncan Laurie <dlaurie@chromium.org> | 2018-12-19 18:05:51 +0000 |
commit | 7f520c8fe6fc991df2c4e91f42843d4290744ebb (patch) | |
tree | a59278cfe21468ca6a0670304adb98f0c01222fe /src/mainboard/google/zoombini/variants/meowth/devicetree.cb | |
parent | cb76069e871d503cd0d1687f87d047d4c7dfea64 (diff) |
zoombini: remove support for deprecated zoombini board
Change-Id: Iab2737940f07afb4f5a29ff50e6cb2a22027c51b
Signed-off-by: Bob Moragues <moragues@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30094
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/zoombini/variants/meowth/devicetree.cb')
-rw-r--r-- | src/mainboard/google/zoombini/variants/meowth/devicetree.cb | 204 |
1 files changed, 0 insertions, 204 deletions
diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb deleted file mode 100644 index b014353e0b..0000000000 --- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb +++ /dev/null @@ -1,204 +0,0 @@ -chip soc/intel/cannonlake - - # Deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" - - # Debug Option - register "DebugConsent" = "DebugConsent_Disabled" - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "gpe0_dw0" = "PMC_GPP_A" - register "gpe0_dw1" = "PMC_GPP_B" - register "gpe0_dw2" = "PMC_GPP_C" - - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - - device cpu_cluster 0 on - device lapic 0 on end - end - - # FSP configuration - register "SaGv" = "SaGv_Enabled" - register "ScsEmmcHs400Enabled" = "1" - - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| GSPI0 | cr50 TPM. Early init is | - #| | required to set up a BAR | - #| | for TPM communication | - #| | before memory is up | - #| I2C0 | Touchscreen Digitizer | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .gspi[0] = { - .speed_mhz = 1, - .early_init = 1, - }, - .i2c[0] = { - .speed = I2C_SPEED_FAST_PLUS, - .rise_time_ns = 98, - .fall_time_ns = 38, - }, - }" - - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC3)" - register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" - register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" - register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" - register "usb2_ports[6]" = "USB2_PORT_TYPE_C(OC_SKIP)" - register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)" - register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" - register "usb2_ports[9]" = "USB2_PORT_TYPE_C(OC_SKIP)" - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" - - register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkSsp0" = "1" - register "PchHdaAudioLinkSsp1" = "1" - - # Enable cpufreq - register "speed_shift_enable" = "1" - - # Enable Root port 8 (PCIe port 9) for NVMe - register "PcieRpEnable[8]" = "1" - register "PcieClkSrcUsage[3]" = "8" - register "PcieClkSrcClkReq[3]" = "3" - - # Enable S0ix - register "s0ix_enable" = "1" - - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - chip drivers/intel/wifi - register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - end - device pci 14.5 off end # SDCard - device pci 15.0 on - chip drivers/i2c/hid - register "generic.hid" = ""WCOM50C1"" - register "generic.desc" = ""WCOM Digitizer"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C14_IRQ)" - register "generic.speed" = "I2C_SPEED_FAST_PLUS" - register "hid_desc_reg_offset" = "0x1" - device i2c 0a on end - end - end # I2C #0 - device pci 15.1 on - chip drivers/i2c/generic - register "hid" = ""STH9310"" - register "name" = ""SEMTECH SX9310"" - register "desc" = ""Left SAR Proximity Sensor"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C3_IRQ)" - register "speed" = "I2C_SPEED_FAST_PLUS" - register "uid" = "1" - device i2c 28 on end - end - end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 on - chip drivers/i2c/max98373 - register "vmon_slot_no" = "4" - register "imon_slot_no" = "5" - register "uid" = "0" - register "desc" = ""RIGHT SPEAKER AMP"" - register "name" = ""MAXR"" - device i2c 31 on end - end - chip drivers/i2c/max98373 - register "vmon_slot_no" = "6" - register "imon_slot_no" = "7" - register "uid" = "1" - register "desc" = ""LEFT SPEAKER AMP"" - register "name" = ""MAXL"" - device i2c 32 on end - end - end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 off end # SATA - device pci 19.0 on end # I2C #4 - device pci 19.1 on - chip drivers/i2c/generic - register "hid" = ""STH9310"" - register "name" = ""SEMTECH SX9310"" - register "desc" = ""Right SAR Proximity Sensor"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C4_IRQ)" - register "speed" = "I2C_SPEED_FAST_PLUS" - register "uid" = "0" - device i2c 28 on end - end - end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 on - chip drivers/spi/acpi - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "compat_string" = ""google,cr50"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C12_IRQ)" - device spi 0 on end - end - end # GSPI #0 - device pci 1e.3 on - chip drivers/spi/acpi - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "uid" = "1" - register "compat_string" = ""google,cros-ec-spi"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A22_IRQ)" - device spi 0 on end - end - end # GSPI #1 - device pci 1f.0 on - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end |