diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-08-20 14:06:13 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-08-28 15:15:26 +0000 |
| commit | 903c9764a16fba61bf90187d6f7e2afde37cfec0 (patch) | |
| tree | 613569c7c546b90d941d55374b3f80fa59f30bf8 /src/mainboard/google/zoombini/romstage.c | |
| parent | 5dff396befca2241f8323b422cbf6cc5b66a7488 (diff) | |
soc/intel/cannonlake: Change LPDDR4 to MEMCFG
Modify the previously SOC_CNL_LPDDR4_INIT to SOC_CNL_MEMCFG_INIT, to
make the infrasturture to handle both LPDDR4 and DDR4 cases in the
future. Consider the case of reading SPD from SMBus other than providing
SPD pointer directly.
BUG=N/A
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.
Change-Id: I2f898147f67dd52b89cc3d9fc4e6b3854fa81f57
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28248
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/zoombini/romstage.c')
| -rw-r--r-- | src/mainboard/google/zoombini/romstage.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/zoombini/romstage.c b/src/mainboard/google/zoombini/romstage.c index 8e191776d0..4bd0ede14f 100644 --- a/src/mainboard/google/zoombini/romstage.c +++ b/src/mainboard/google/zoombini/romstage.c @@ -14,7 +14,7 @@ */ #include <baseboard/variants.h> -#include <soc/cnl_lpddr4_init.h> +#include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> void mainboard_memory_init_params(FSPM_UPD *memupd) @@ -24,6 +24,6 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) .spd_spec.spd_index = variant_memory_sku(), }; - cannonlake_lpddr4_init(&memupd->FspmConfig, + cannonlake_memcfg_init(&memupd->FspmConfig, variant_lpddr4_config(), &spd); } |