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authorNick Vaccaro <nvaccaro@chromium.org>2017-12-22 23:01:00 -0800
committerDuncan Laurie <dlaurie@chromium.org>2018-01-09 18:19:32 +0000
commit38fcc8ab5022558928e0cb464b50ebd02ee67c21 (patch)
tree85bd1e530a5ddd3b055bb9ab3ab6345bf1b9ceeb /src/mainboard/google/zoombini/Kconfig
parentb3585b9b351adbce05515581e13a6039f8cd4dd3 (diff)
mainboard/google/zoombini: Provide memory configuration variant API
Add support for memory configuration by providing weak implementation from the baseboard. All SPD files are present under spd/ directory. SPD_SOURCES must be provided by the variants to ensure that required SPD hex files are included in the SPD binary. BUG=b:64395641 BRANCH=None TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: I449ab56dfc7a75752944b58ba6291b5ee32f81ad Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://review.coreboot.org/22205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard/google/zoombini/Kconfig')
-rw-r--r--src/mainboard/google/zoombini/Kconfig5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/zoombini/Kconfig b/src/mainboard/google/zoombini/Kconfig
index efa2d9ca7a..d6c125091e 100644
--- a/src/mainboard/google/zoombini/Kconfig
+++ b/src/mainboard/google/zoombini/Kconfig
@@ -8,6 +8,7 @@ config BOARD_GOOGLE_BASEBOARD_ZOOMBINI
select HAVE_ACPI_TABLES
select MAINBOARD_HAS_CHROMEOS
select SOC_INTEL_CANNONLAKE
+ select SOC_INTEL_CANNONLAKE_LPDDR4_INIT
if BOARD_GOOGLE_BASEBOARD_ZOOMBINI
@@ -19,6 +20,10 @@ config DEVICETREE
string
default "variants/baseboard/devicetree.cb"
+config DIMM_SPD_SIZE
+ int
+ default 512
+
config DRIVER_TPM_I2C_BUS
depends on ZOOMBINI_USE_I2C_TPM
default 0x1