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authorNick Chen <nick_xr_chen@wistron.corp-partner.google.com>2020-11-12 18:18:33 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-11-16 11:03:50 +0000
commitb7a55fd804c1339215f54a34b6920f92cc48cf75 (patch)
treec654d119494a0c82fcf8f967ad261db6e60b72c7 /src/mainboard/google/volteer
parente41f595310d6e74ba8ca67c87abfa2fed790428f (diff)
volteer/variants/eldrid: Goodix touch panel power-on sequence tuning
1. Enable panel stop GPIO in ramstage 2. generic.reset_delay_ms change to 30 BUG=b:171365316 Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> Change-Id: I90ca39312252c668da6298183e598392bc9f9f28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
Diffstat (limited to 'src/mainboard/google/volteer')
-rw-r--r--src/mainboard/google/volteer/variants/eldrid/gpio.c2
-rw-r--r--src/mainboard/google/volteer/variants/eldrid/overridetree.cb2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/volteer/variants/eldrid/gpio.c b/src/mainboard/google/volteer/variants/eldrid/gpio.c
index 3d627e3b81..24f80a05b8 100644
--- a/src/mainboard/google/volteer/variants/eldrid/gpio.c
+++ b/src/mainboard/google/volteer/variants/eldrid/gpio.c
@@ -80,7 +80,7 @@ static const struct pad_config override_gpio_table[] = {
/* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
/* E3 : CPU_GP0 ==> USI_REPORT_EN */
- PAD_CFG_GPO(GPP_E3, 1, DEEP),
+ PAD_CFG_GPO(GPP_E3, 0, DEEP),
/* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */
PAD_CFG_GPI(GPP_E4, NONE, DEEP),
/* E6 : THC0_SPI1_RST# ==> GPP_E6_STRAP */
diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb
index f9ab7c95d3..72571c039a 100644
--- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb
@@ -123,7 +123,7 @@ chip soc/intel/tigerlake
register "generic.probed" = "1"
register "generic.reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
- register "generic.reset_delay_ms" = "120"
+ register "generic.reset_delay_ms" = "30"
register "generic.reset_off_delay_ms" = "3"
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)"
register "generic.enable_delay_ms" = "12"