diff options
| author | Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> | 2020-10-21 11:16:08 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-26 06:43:20 +0000 |
| commit | d3108d6c898e7789dc7e5c193158476bca7c4a6e (patch) | |
| tree | bb552680046773add92f8b44d3d5719868006d17 /src/mainboard/google/volteer | |
| parent | 9572dd895324ae18c186b1238770422b2d9240a6 (diff) | |
mb/google/volteer/var/voxel: Disable SRCCLKREQ1#
According to the schematic,SRCCLKREQ1# is not connected,so disable it
on voxel.
BUG=b:171279034
BRANCH=volteer
TEST="emerge-volteer coreboot" compiles successfully.
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ibc4f766bd737f30a9ac3c7354d54398e0c36d59d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46612
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/volteer')
| -rw-r--r-- | src/mainboard/google/volteer/variants/voxel/overridetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index d7a265b010..e8be8e3eb3 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -14,6 +14,9 @@ chip soc/intel/tigerlake .tdp_pl4 = 105, }" + # Disable SRCCLKREQ1# + register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + device domain 0 on device ref dptf on chip drivers/intel/dptf |