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authorDavid Wu <david_wu@quanta.corp-partner.google.com>2020-09-04 20:50:12 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-09-14 07:04:34 +0000
commita545d3083183fb3cab28306e35ec765c906c1a5b (patch)
treee35d1c4e4be0969b64521708326da95936be71df /src/mainboard/google/volteer/variants
parenta5cb5649fb106351d9740ebb6ebe0b3113c84def (diff)
mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset
1. Set tcc offset to 5 degree celsius 2. Apply the DPTF parameters received from the thermal team. BUG=b:167523658 TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I01a6fc5bd959798c8dd423df3907c69c883733e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/volteer/variants')
-rw-r--r--src/mainboard/google/volteer/variants/voxel/overridetree.cb62
1 files changed, 62 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb
index 43296d585f..330d852375 100644
--- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb
@@ -1,5 +1,67 @@
chip soc/intel/tigerlake
+ register "tcc_offset" = "5" # TCC of 95
+
+ register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
+ .tdp_pl1_override = 18,
+ .tdp_pl2_override = 51,
+ .tdp_pl4 = 71,
+ }"
+ register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
+ .tdp_pl1_override = 18,
+ .tdp_pl2_override = 51,
+ .tdp_pl4 = 105,
+ }"
+
device domain 0 on
+ device pci 04.0 on
+ chip drivers/intel/dptf
+ ## Active Policy
+ register "policies.active" = "{
+ [0] = {.target = DPTF_CPU,
+ .thresholds = {TEMP_PCT(94, 100),}},
+ [1] = {.target = DPTF_TEMP_SENSOR_2,
+ .thresholds = {TEMP_PCT(64, 100),
+ TEMP_PCT(60, 90),
+ TEMP_PCT(56, 80),
+ TEMP_PCT(52, 70),
+ TEMP_PCT(48, 60),
+ TEMP_PCT(44, 50),
+ TEMP_PCT(40, 40),}}}"
+
+ ## Passive Policy
+ register "policies.passive" = "{
+ [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
+ [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000),
+ [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000),
+ [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 54, 6000),
+ [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}"
+
+ ## Critical Policy
+ register "policies.critical" = "{
+ [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN),
+ [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN),
+ [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN),
+ [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN),
+ [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)}"
+
+ ## Power Limits Control
+ # 12-18W PL1 in 200mW increments, avg over 28-32s interval
+ # PL2 is fixed at 51W, avg over 28-32s interval
+ register "controls.power_limits" = "{
+ .pl1 = {.min_power = 12000,
+ .max_power = 18000,
+ .time_window_min = 28 * MSECS_PER_SEC,
+ .time_window_max = 32 * MSECS_PER_SEC,
+ .granularity = 200,},
+ .pl2 = {.min_power = 15000,
+ .max_power = 51000,
+ .time_window_min = 28 * MSECS_PER_SEC,
+ .time_window_max = 32 * MSECS_PER_SEC,
+ .granularity = 1000,}}"
+
+ device generic 0 on end
+ end
+ end # DPTF 0x9A03
device pci 15.0 on
chip drivers/i2c/generic
register "hid" = ""10EC5682""