diff options
| author | Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> | 2021-04-20 12:19:16 +0800 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2021-04-21 17:08:30 +0000 |
| commit | a5761efd14a20b2eb419f27bb8142ae04f1b326e (patch) | |
| tree | aa332700e87bf3b37ac7368d2624307b897782b5 /src/mainboard/google/volteer/variants | |
| parent | a590852313359d31ae1cfb0093daf4fe3610262a (diff) | |
mb/google/volteer/variants/drobit: Update DPTF parameters
Update the DPTF parameters. Modify TDP, Critical Policy and Active Policy setting.
BUG=b:177777472
BRANCH=firmware-volteer-13672.B
TEST=build test firmware and verified by thermal team.
Change-Id: Ib57de5535f3d37765ac7051c17445c311c098927
Signed-off-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/mainboard/google/volteer/variants')
| -rw-r--r-- | src/mainboard/google/volteer/variants/drobit/overridetree.cb | 18 |
1 files changed, 8 insertions, 10 deletions
diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb index 87c1417261..5525205d96 100644 --- a/src/mainboard/google/volteer/variants/drobit/overridetree.cb +++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb @@ -5,7 +5,7 @@ chip soc/intel/tigerlake register "tcc_offset" = "8" register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ - .tdp_pl1_override = 13, + .tdp_pl1_override = 9, .tdp_pl2_override = 28, .tdp_pl4 = 105, }" @@ -63,22 +63,20 @@ chip soc/intel/tigerlake ## Active Policy register "policies.active" = "{ [0] = {.target = DPTF_TEMP_SENSOR_1, - .thresholds = {TEMP_PCT(49, 90), - TEMP_PCT(46, 80), - TEMP_PCT(45, 70), - TEMP_PCT(44, 65), - TEMP_PCT(42, 57), - TEMP_PCT(40, 50),}}}" + .thresholds = {TEMP_PCT(49, 80), + TEMP_PCT(46, 70), + TEMP_PCT(44, 60), + TEMP_PCT(42, 50),}}}" ## Critical Policy register "policies.critical" = "{ - [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN)}" + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN)}" ## Power Limits Control - # 13-17W PL1 in 125mW increments, avg over 28-32s interval + # 9-17W PL1 in 125mW increments, avg over 28-32s interval # PL2 is 28-64W, avg over 28-32s interval register "controls.power_limits" = "{ - .pl1 = {.min_power = 13000, + .pl1 = {.min_power = 9000, .max_power = 17000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, |