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authorDavid Wu <david_wu@quanta.corp-partner.google.com>2020-10-21 10:42:25 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-10-26 06:43:45 +0000
commit7d1a137b845ad0b4d1aa1553070b26411b899cf6 (patch)
tree8388c4a24c83e669cd081c7e783f41bf72c29058 /src/mainboard/google/volteer/variants
parente738a7e337a7446a7dee6e1ddb540c4fa4919a26 (diff)
mb/google/volteer: Use PCIE_CLK_NOTUSED in place of 0xFF
Use PCIE_CLK_NOTUSED in place of 0xFF for unused PCIe ports BUG=none BRANCH=master TEST="emerge-volteer coreboot" compiles successfully. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I35f2bbce35420fa98541a35f77b14df7440e7980 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/google/volteer/variants')
-rw-r--r--src/mainboard/google/volteer/variants/baseboard/devicetree.cb8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 7486aef84c..b76f627873 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -103,10 +103,10 @@ chip soc/intel/tigerlake
register "PcieClkSrcClkReq[1]" = "1"
# Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality
- register "PcieClkSrcUsage[2]" = "0xFF"
- register "PcieClkSrcUsage[4]" = "0xFF"
- register "PcieClkSrcUsage[5]" = "0xFF"
- register "PcieClkSrcUsage[6]" = "0xFF"
+ register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED"
+ register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED"
+ register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED"
+ register "PcieClkSrcUsage[6]" = "PCIE_CLK_NOTUSED"
# Enable SATA
register "SataEnable" = "1"