diff options
| author | Duncan Laurie <dlaurie@google.com> | 2020-10-28 14:26:26 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2020-11-20 00:27:04 +0000 |
| commit | 2b3de787a49e4a1ab0e47e9c6ce1115548ed3287 (patch) | |
| tree | 29f8836b1eeb4d523eb0c604cc1587d28c4ec609 /src/mainboard/google/volteer/variants | |
| parent | 7f6a4845110cc74a97428b321627454e02c8d2fe (diff) | |
mb/google/volteer/variants: Set TCSS PCIe RP0 to hidden by default
Set the default state of the TCSS PCIe RP0 to hidden so that coreboot
does not allocate resources to this hotplug root port. The default
behavior on the reference design is that there is only one USB4 port
attached to port C1 while port C0 is only a USB3 port.
Meanwhile the Voxel and Terrador variants do have USB4 on both C0 and
C1 ports, so these boards change the default to 'on' so that coreboot
does allocate resources for the hotplug port.
BUG=b:159143739
BRANCH=volteer
TEST=build volteer and voxel and check the resulting static.c to
ensure the device is hidden or not. Also boot with the two different
configurations and ensure resources are assigned or not. Finally
check that S0ix still functions with the C0 port set to 'hidden'
after authorizing a PCIe tunnel on port C1.
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I8bb05ae8cd14412854212b7ed189cfa43d602c1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47198
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/volteer/variants')
3 files changed, 14 insertions, 1 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index fa807ba40f..bc93ec96bd 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -414,7 +414,10 @@ chip soc/intel/tigerlake device generic 0 on end end end # DPTF 0x9A03 - device ref tbt_pcie_rp0 on + # Volteer reference design does not have PCIe on Type-C port C0 so it should + # not have hotplug resources allocated. Marking the device hidden will ensure + # it is still enabled so it can participate in power management. + device ref tbt_pcie_rp0 hidden probe DB_USB USB4_GEN2 probe DB_USB USB4_GEN3 end diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index 87959b8798..2a5b98d891 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -187,6 +187,11 @@ chip soc/intel/tigerlake device generic 0 on end end end + # This variant has USB4/PCIe on both ports so RP0 must be enabled + # in order for hotplug resources to be assigned to Type-C Port C0. + device ref tbt_pcie_rp0 on + probe DB_USB USB4_GEN3 + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index cdbde983fd..dd29553e82 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -202,6 +202,11 @@ chip soc/intel/tigerlake device generic 0 on end end end + # This variant has USB4/PCIe on both ports so RP0 must be enabled + # in order for hotplug resources to be assigned to Type-C Port C0. + device ref tbt_pcie_rp0 on + probe DB_USB USB4_GEN3 + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. |