diff options
| author | Jes Klinke <jbk@google.com> | 2020-10-14 16:25:47 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-02 06:28:00 +0000 |
| commit | fbb568347de2037e64e894e2ec68c61ff3de73c8 (patch) | |
| tree | a9d67502c60f39d2e171c9ea3f233f7d403faf62 /src/mainboard/google/volteer/variants/volteer2/overridetree.cb | |
| parent | 49da0cfe4681f883d7be9ee68c7d4de1108eb0cc (diff) | |
mb/google/volteer: New variant for Volteer reworked with Dauntless
For development of the firmware to run on the Dauntless TPM, a number of
Volteer2 devices are being reworked to replace the H1 chip with probe
wires to connect to an external Dauntless development board.
Some modification to the AP firmware is required, not least because the
Dauntless chip is connected via I2C bus, instead of SPI. Most of the
Dauntless developers will not otherwise have a Chrome OS chroot.
Because of the above, I think it makes sense to have a new variant, for
the reworked devices, which I intend to create with this CL.
BUG=b:169526865
TEST=abuild -t GOOGLE_VOLTEER2_TI50 -c max -x
Change-Id: Ibdcd6c2ce3941c229518f21f0e479890b5d76dd1
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/volteer/variants/volteer2/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/volteer/variants/volteer2/overridetree.cb | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index a36a8441b4..502883eee8 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -56,6 +56,32 @@ chip soc/intel/tigerlake register "FastPkgCRampDisable[VR_DOMAIN_SA]" = "1" register "FastPkgCRampDisable[VR_DOMAIN_VLCC]" = "1" + # Depending on whether we use I2C bus 1 or SPI bus 0 for TPM + # communication, that one needs early initialization. + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = CONFIG(MAINBOARD_HAS_SPI_TPM_CR50), + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .early_init = CONFIG(MAINBOARD_HAS_I2C_TPM_CR50), + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on device ref dptf on chip drivers/intel/dptf |