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authorJes Klinke <jbk@google.com>2020-10-14 16:25:47 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-11-02 06:28:00 +0000
commitfbb568347de2037e64e894e2ec68c61ff3de73c8 (patch)
treea9d67502c60f39d2e171c9ea3f233f7d403faf62 /src/mainboard/google/volteer/variants/volteer2/gpio.c
parent49da0cfe4681f883d7be9ee68c7d4de1108eb0cc (diff)
mb/google/volteer: New variant for Volteer reworked with Dauntless
For development of the firmware to run on the Dauntless TPM, a number of Volteer2 devices are being reworked to replace the H1 chip with probe wires to connect to an external Dauntless development board. Some modification to the AP firmware is required, not least because the Dauntless chip is connected via I2C bus, instead of SPI. Most of the Dauntless developers will not otherwise have a Chrome OS chroot. Because of the above, I think it makes sense to have a new variant, for the reworked devices, which I intend to create with this CL. BUG=b:169526865 TEST=abuild -t GOOGLE_VOLTEER2_TI50 -c max -x Change-Id: Ibdcd6c2ce3941c229518f21f0e479890b5d76dd1 Signed-off-by: Jes Bodi Klinke <jbk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/volteer/variants/volteer2/gpio.c')
-rw-r--r--src/mainboard/google/volteer/variants/volteer2/gpio.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/volteer2/gpio.c b/src/mainboard/google/volteer/variants/volteer2/gpio.c
index 6c67fc216e..069b2f0a98 100644
--- a/src/mainboard/google/volteer/variants/volteer2/gpio.c
+++ b/src/mainboard/google/volteer/variants/volteer2/gpio.c
@@ -243,6 +243,11 @@ static const struct pad_config early_gpio_table[] = {
/* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */
PAD_CFG_GPO(GPP_H11, 1, DEEP),
+
+ /* The two signals used for I2C communication with Ti50 on the
+ * volteer2_ti50 variant. */
+ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* PCH_I2C1_TOUCH_USI_SDA */
+ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* PCH_I2C1_TOUCH_USI_SCL */
};
const struct pad_config *variant_override_gpio_table(size_t *num)