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authorShreesh Chhabbi <shreesh.chhabbi@intel.com>2020-06-17 12:40:42 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-07-14 16:07:25 +0000
commit370868766b90ce4bfa0342b6266a232b5326df50 (patch)
tree410a6d2d14072ec9a2c2a54e3ab5139a6f1b7f82 /src/mainboard/google/volteer/variants/malefor
parent8cf43f6c98346fdfa58f978c68371c51f0f99e16 (diff)
mainboard/volteer: Enable SaGv for volteer2, delbin & voxel
SaGv needs to be enabled for only QS. On ES2, we are seeing system instability. BUG=b:159198381 TEST=Tested for boot. Power and performance tests were run with volteer2 with qs setup. System showed stability. Tested for boot stability on on delbin. Change-Id: I1bce3b9f837fb19ba5a20ae31750a73474a86788 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
Diffstat (limited to 'src/mainboard/google/volteer/variants/malefor')
-rw-r--r--src/mainboard/google/volteer/variants/malefor/overridetree.cb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/malefor/overridetree.cb b/src/mainboard/google/volteer/variants/malefor/overridetree.cb
index b2a658c16f..c84ed833c5 100644
--- a/src/mainboard/google/volteer/variants/malefor/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/malefor/overridetree.cb
@@ -17,6 +17,8 @@ chip soc/intel/tigerlake
register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A / Type-C Not Used
+ register "SaGv" = "SaGv_Disabled"
+
# I2C Port Config
register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,