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authorWilliam Wei <wenxu.wei@bitland.corp-partner.google.com>2020-03-26 14:18:53 +0800
committerFurquan Shaikh <furquan@google.com>2020-04-02 06:46:38 +0000
commitda1b088885b12e5b20afd5dd99e31acf3c41965b (patch)
tree2241052416fc1b514117efdf8015786d464de00c /src/mainboard/google/volteer/variants/malefor/memory.c
parentce482849782715bd048faba89f86bfa0aee75598 (diff)
mb/google/volteer: Create Malefor variant
This commit creates a malefor variant for Volteer. The initial settings override the baseboard was copied from variant ripto. Fine tune GPIO and memory DQ based on malefor schematics. BUG=b:150653745 BRANCH=volteer TEST=emerge-volteer coreboot Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com> Change-Id: Idbeebb13e537287686344740211143df35b7863a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39857 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/volteer/variants/malefor/memory.c')
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1 files changed, 40 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/malefor/memory.c b/src/mainboard/google/volteer/variants/malefor/memory.c
new file mode 100644
index 0000000000..75ac762a47
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/malefor/memory.c
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <baseboard/variants.h>
+
+static const struct mb_lpddr4x_cfg malefor_memcfg = {
+ /* DQ byte map */
+ .dq_map = {
+ { 3, 1, 0, 2, 4, 6, 7, 5, /* Byte 0 */
+ 12, 13, 14, 15, 8, 9, 10, 11 }, /* Byte 1 */
+ { 0, 7, 1, 6, 2, 4, 3, 5, /* Byte 2 */
+ 8, 15, 14, 9, 13, 10, 12, 11 }, /* Byte 3 */
+ { 3, 2, 0, 1, 4, 5, 6, 7, /* Byte 4 */
+ 12, 13, 15, 14, 8, 9, 10, 11 }, /* Byte 5 */
+ { 6, 0, 1, 7, 5, 4, 2, 3, /* Byte 6 */
+ 15, 14, 8, 9, 10, 12, 11, 13 }, /* Byte 7 */
+ { 5, 0, 1, 3, 4, 2, 7, 6, /* Byte 0 */
+ 11, 14, 13, 12, 8, 9, 15, 10 }, /* Byte 1 */
+ { 3, 4, 2, 5, 0, 6, 1, 7, /* Byte 2 */
+ 13, 12, 11, 10, 14, 15, 9, 8 }, /* Byte 3 */
+ { 3, 2, 1, 0, 5, 4, 7, 6, /* Byte 4 */
+ 12, 13, 15, 14, 8, 11, 9, 10 }, /* Byte 5 */
+ { 3, 4, 2, 5, 1, 0, 7, 6, /* Byte 6 */
+ 15, 14, 9, 8, 12, 10, 11, 13 } /* Byte 7 */
+ },
+
+ /* DQS CPU<>DRAM map */
+ .dqs_map = {
+ /* Ch 0 1 2 3 */
+ { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
+ { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }
+ },
+
+ .ect = 0, /* Disable Early Command Training */
+};
+
+const struct mb_lpddr4x_cfg *variant_memory_params(void)
+{
+ return &malefor_memcfg;
+}