diff options
| author | Frank Wu <frank_wu@compal.corp-partner.google.com> | 2020-08-11 16:04:45 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-08-12 19:42:48 +0000 |
| commit | 1d7ba15aa2e3a3ee9130101977405ef866bd7f79 (patch) | |
| tree | 4415c24df0319fa9a145897bbbac5fa569adde1a /src/mainboard/google/volteer/variants/halvor/overridetree.cb | |
| parent | e915cfc0d8b803a9034a4d7e3fb4d8ca76556ab3 (diff) | |
mb/google/volteer/halvor: Update settings for WiFi/BT functions
Configure gpio/overridetree settings for WiFi/BT functions.
Then WiFi/BT functions are enabled on Halvor.
BUG=b:153680359, b:163004808
TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage
Verify that WiFi/BT can scan devices successfully.
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I085b192bb768c2c1238f3f857d315502ac10857e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44372
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/volteer/variants/halvor/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/volteer/variants/halvor/overridetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/volteer/variants/halvor/overridetree.cb b/src/mainboard/google/volteer/variants/halvor/overridetree.cb index 12e059c100..c6ac1b7173 100644 --- a/src/mainboard/google/volteer/variants/halvor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/halvor/overridetree.cb @@ -8,7 +8,7 @@ chip soc/intel/tigerlake register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Reserve for CNVi BT register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1 |