mb/google/volteer: Use device aliases

Use the device aliases provided by tigerlake chipset.cb instead of
the raw pci device+function.  Take advantage of the default states
in chipset.cb and only list the devices that are enabled for all
volteer variants.

Change-Id: I5620004afd7fa4d50389f32dd79148960a2b2662
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44039
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 26 insertions, 80 deletions

diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 7790230b39..e428588c35 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -320,10 +320,8 @@ chip soc/intel/tigerlake
 	}"
 
 	device domain 0 on
-		#From EDS(575683)
-		device pci 00.0 on  end # Host Bridge			0x9A14:U/0x9A12:Y
-		device pci 02.0 on  end # Graphics
-		device pci 04.0 on
+		device ref igpu on end
+		device ref dptf on
 			# Default DPTF Policy for all Volteer boards if not overridden
 			chip drivers/intel/dptf
 				## Active Policy
@@ -417,90 +415,44 @@ chip soc/intel/tigerlake
 				device generic 0 on end
 			end
 		end # DPTF				0x9A03
-		device pci 05.0 off end # IPU				0x9A19
-		device pci 06.0 off end # PEG60				0x9A09
-		device pci 07.0 on	# TBT_PCIe0			0x9A23
+		device ref tbt_pcie_rp0 on
 			probe DB_USB USB4_GEN2
 			probe DB_USB USB4_GEN3
 		end
-		device pci 07.1 on	# TBT_PCIe1			0x9A25
+		device ref tbt_pcie_rp1 on
 			probe DB_USB USB4_GEN2
 			probe DB_USB USB4_GEN3
 		end
-		device pci 07.2 off end # TBT_PCIe2			0x9A27
-		device pci 07.3 off end # TBT_PCIe3			0x9A29
-		device pci 08.0 on  end # GNA				0x9A11
-		device pci 09.0 off end # NPK				0x9A33
-		device pci 0a.0 off end # Crash-log SRAM		0x9A0D
-		device pci 0d.0 on  end # USB xHCI			0x9A13
-		device pci 0d.1 off end # USB xDCI (OTG)		0x9A15
-		device pci 0d.2 on	# TBT DMA0			0x9A1B
+		device ref tbt_dma0 on
 			probe DB_USB USB4_GEN2
 			probe DB_USB USB4_GEN3
 		end
-		device pci 0d.3 off end # TBT DMA1			0x9A1D
-		device pci 0e.0 off end # VMD				0x9A0B
-
-		# From PCH EDS(576591)
-		device pci 10.2 on  end # CNVi: BT			0xA0F5 - A0F7
-		device pci 10.6 off end # THC0				0xA0D0
-		device pci 10.7 off end # THC1				0xA0D1
-
-		device pci 12.0 off end # SensorHUB			0xA0FC
-		device pci 12.6 off end # GSPI2				0x34FB
-
-		device pci 13.0 off end # GSPI3				0xA0FD
-
-		device pci 14.0 on  end # USB3.1 xHCI			0xA0ED
-		device pci 14.1 off end # USB3.1 xDCI			0xA0EE
-		device pci 14.2 on  end # Shared RAM			0xA0EF
+		device ref gna on end
+		device ref north_xhci on end
+		device ref cnvi_bt on end
+		device ref south_xhci on end
+		device ref shared_ram on end
 		chip drivers/intel/wifi
 			register "wake" = "GPE0_PME_B0"
-			device pci 14.3 on end # CNVi: WiFi		0xA0F0 - A0F3
+			device ref cnvi_wifi on end
 		end
-		device pci 15.0 on  end # I2C #0			0xA0E8
-		device pci 15.1 on  end # I2C1				0xA0E9
-		device pci 15.2 on  end # I2C2				0xA0EA
-		device pci 15.3 on  end # I2C3				0xA0EB
-
-		device pci 16.0 on  end # HECI1				0xA0E0
-		device pci 16.1 off end # HECI2				0xA0E1
-		device pci 16.2 off end # CSME				0xA0E2
-		device pci 16.3 off end # CSME				0xA0E3
-		device pci 16.4 off end # HECI3				0xA0E4
-		device pci 16.5 off end # HECI4				0xA0E5
-
-		device pci 17.0 on  end # SATA				0xA0D3
-
-		device pci 19.0 on  end # I2C4				0xA0C5
-		device pci 19.1 on  end # I2C5				0xA0C6
-		device pci 19.2 off end # UART2				0xA0C7
-
-		device pci 1c.0 on  end # RP1				0xA0B8
-		device pci 1c.1 off end # RP2				0xA0B9
-		device pci 1c.2 off end # RP3				0xA0BA
-		device pci 1c.3 off end # RP4				0xA0BB
-		device pci 1c.4 off end # RP5				0xA0BC
-		device pci 1c.5 off end # WWAN RP6			0xA0BD
-		device pci 1c.6 on  end # RP7				0xA0BE
-		device pci 1c.7 on  end # SD Card RP8			0xA0BF
-
-		device pci 1d.0 on  end # RP9				0xA0B0
-		device pci 1d.1 off end # RP10				0xA0B1
-		device pci 1d.2 on  end # RP11				0xA0B2
-		device pci 1d.3 off end # RP12				0xA0B3
-
-		device pci 1e.0 on  end # UART0				0xA0A8
-		device pci 1e.1 off end # UART1				0xA0A9
-		device pci 1e.2 on
+		device ref heci1 on end
+		device ref sata on end
+		device ref pcie_rp1 on end
+		device ref pcie_rp7 on end
+		device ref pcie_rp8 on end
+		device ref pcie_rp9 on end
+		device ref pcie_rp11 on end
+		device ref uart0 on end
+		device ref gspi0 on
 			chip drivers/spi/acpi
 				register "hid" = "ACPI_DT_NAMESPACE_HID"
 				register "compat_string" = ""google,cr50""
 				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)"
 				device spi 0 on end
 			end
-		end # GSPI0						0xA0AA
-		device pci 1e.3 on
+		end
+		device ref gspi1 on
 			chip drivers/spi/acpi
 				register "name" = ""CRFP""
 				register "hid" = "ACPI_DT_NAMESPACE_HID"
@@ -509,18 +461,12 @@ chip soc/intel/tigerlake
 				register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_C20)"
 				device spi 0 on end
 			end # FPMCU
-		end # GSPI1						0xA0AB
-		device pci 1f.0 on
+		end
+		device ref pch_espi on
 			chip ec/google/chromeec
 				device pnp 0c09.0 on end
 			end
-		end # eSPI						0xA080 - A09F
-		device pci 1f.1 off end # P2SB				0xA0A0
-		device pci 1f.2 hidden end # PMC			0xA0A1
-		device pci 1f.3 on  end # Intel HD audio		0xA0C8-A0CF
-		device pci 1f.4 off end # SMBus				0xA0A3
-		device pci 1f.5 on  end # SPI				0xA0A4
-		device pci 1f.6 off end # GbE				0x15E1/0x15E2
-		device pci 1f.7 off end # TH				0xA0A6
+		end
+		device ref hda on end
 	end
 end