diff options
| author | John Zhao <john.zhao@intel.com> | 2020-05-13 16:44:38 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-06-02 04:41:42 +0000 |
| commit | 5d79a0cc5ad7e58b240be3d3531bfa1df225534d (patch) | |
| tree | 7e45334f4c0e002debb78b65b5a38750278e812d /src/mainboard/google/volteer/variants/baseboard/devicetree.cb | |
| parent | f219b6a2b9f9528e4a182d9b035af900ae740c2a (diff) | |
mb/google/volteer: Enable TCSS DMA0 for Volteer
This explicitly enables TCSS DMA0 controller and disables
TBT PCIe2 and PCIE3 since they are unused on volteer.
BUG=:b:146624360
TEST=Built and booted on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I05cc9e3964d8037d433fca443be6e8d5b444bbce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41387
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/volteer/variants/baseboard/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index c6a2e8b1a6..b7f2a0a3de 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -132,7 +132,6 @@ chip soc/intel/tigerlake register "IomTypeCPortPadCfg[6]" = "0x0" register "IomTypeCPortPadCfg[7]" = "0x0" - # D3Hot and D3Cold for TCSS register "TcssD3HotEnable" = "1" register "TcssD3ColdEnable" = "1" @@ -227,16 +226,16 @@ chip soc/intel/tigerlake device pci 04.0 on end # DPTF 0x9A03 device pci 05.0 off end # IPU 0x9A19 device pci 06.0 off end # PEG60 0x9A09 - device pci 07.0 on end # TBT_PCIe0 0x9A23 - device pci 07.1 on end # TBT_PCIe1 0x9A25 - device pci 07.2 on end # TBT_PCIe2 0x9A27 - device pci 07.3 on end # TBT_PCIe3 0x9A29 + device pci 07.0 on end # TBT_PCIe0 0x9A23 + device pci 07.1 on end # TBT_PCIe1 0x9A25 + device pci 07.2 off end # TBT_PCIe2 0x9A27 + device pci 07.3 off end # TBT_PCIe3 0x9A29 device pci 08.0 on end # GNA 0x9A11 device pci 09.0 off end # NPK 0x9A33 device pci 0a.0 off end # Crash-log SRAM 0x9A0D device pci 0d.0 on end # USB xHCI 0x9A13 device pci 0d.1 off end # USB xDCI (OTG) 0x9A15 - device pci 0d.2 off end # TBT DMA0 0x9A1B + device pci 0d.2 on end # TBT DMA0 0x9A1B device pci 0d.3 off end # TBT DMA1 0x9A1D device pci 0e.0 off end # VMD 0x9A0B |