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authorJes Klinke <jbk@google.com>2020-10-14 13:24:32 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-10-19 07:03:37 +0000
commit5c80519466863ae7b8579f1edb90829f7f9ee03d (patch)
tree27136cf23aa6d1f844b26dbc2a2958cbeebf16f9 /src/mainboard/google/volteer/mainboard.c
parentd5faa90df50c820ed3b79d4a5e479767efd73287 (diff)
volteer+vendorcode: Retrieve Cr50 version only via SPI
No recent Chromebooks have used I2C for TPM communication, and as a result, a bug has crept in. The ability to extract Cr50 firmware string is only supported via SPI, yet code in mainboard and vendorcode attempt to do so unconditionally. This CL makes it such that the code also compiles for future designs using I2C. (Whether we want to enhance the I2C protocol to be able to provide the version string, and then implement the support is a separate question.) This effort is prompted by the desire to use reworked Volteer EVT devices for validating the new Ti50/Dauntless TPM. Dauntless will primarily be using I2C in upcoming designs. BRANCH=volteer TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x Change-Id: Ida1d732e486b19bdff6d95062a3ac1a7c4b58b45 Signed-off-by: jbk@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/46436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
Diffstat (limited to 'src/mainboard/google/volteer/mainboard.c')
-rw-r--r--src/mainboard/google/volteer/mainboard.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c
index 1fcd5eb5ac..03a78fd777 100644
--- a/src/mainboard/google/volteer/mainboard.c
+++ b/src/mainboard/google/volteer/mainboard.c
@@ -51,7 +51,8 @@ void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *cfg)
return;
}
- if (cr50_is_long_interrupt_pulse_enabled()) {
+ if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50) &&
+ cr50_is_long_interrupt_pulse_enabled()) {
printk(BIOS_INFO, "Enabling S0i3.4\n");
} else {
/*