diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-10-15 18:09:28 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-11-20 00:12:09 +0000 |
| commit | 05c732b9e4c6cac921416d26e9e4febdc63d5772 (patch) | |
| tree | 0ac1b2dd24b87943580a2a19a1916b38b009700f /src/mainboard/google/volteer/dsdt.asl | |
| parent | e593747f061e6e05e8f46d3875be6941c45905f5 (diff) | |
soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPD
Replace the two obsolete LPID implementations with the new PEPD device.
The PEPD device gets included in the plaforms' `southbridge.asl`, since
it is required to load the `intel_pmc_core` module in Linux, which
checks for the _HID. (See CB:46469 for more info on that.)
There is no harm for mainboards not supporting S0ix, because the _DSM
function won't be called with the LPS0 UUID on such boards. Such boards
can use the debugging functionality of `intel_pmc_core`, too.
Change-Id: Ic8427db33286451618b50ca429d41b604dbb08a5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46471
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/volteer/dsdt.asl')
| -rw-r--r-- | src/mainboard/google/volteer/dsdt.asl | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index cf733676e3..ba9541ee5d 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -38,10 +38,6 @@ DefinitionBlock( // Chrome OS specific #include <vendorcode/google/chromeos/acpi/chromeos.asl> - /* Include Low power idle table for a short term workaround to enable - S0ix. Once cr50 pulse width is fixed, this can be removed. */ - #include <soc/intel/common/acpi/lpit.asl> - // Chrome OS Embedded Controller Scope (\_SB.PCI0.LPCB) { |