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authorFurquan Shaikh <furquan@google.com>2021-08-24 00:38:39 -0700
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-09-01 19:19:42 +0000
commitae20d4c78f9fbb5fe9f8c1ef026e159961968f73 (patch)
tree591d2aad48298063ba6ce4d6b0fc0d56450a2901 /src/mainboard/google/volteer/Kconfig
parent9c348a7b7ea3422a74af9b820275751e9abb4a12 (diff)
mb/google/volteer: Fix USB4 enabling for volteer family
volteer baseboard was currently enabling TBT(USB4) devices in baseboard devicetree and also selecting the Kconfigs required for resource allocation above 4G for the USB4 controllers. However, not all volteer devices have USB4 support. This change fixes USB4 enabling for volteer family by making the following udpates: 1. TBT devices are moved from baseboard devicetree to individual override trees for the variants that actually support USB4. 2. When moving TBT devices to override tree, tbt_pcie_rp0 is marked as on instead of hidden for all variants other than volteer reference. This is because volteer reference is the only device that has an asymmetric support for USB4 (i.e. does not support USB4 on C0 port). 3. Kconfig selection for PCIEXP_HOTPLUG is moved to Kconfig.name for these variants. Change-Id: If380dcb1ea1633b3a1d6932e769cb6ed0a2761c7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57112 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/volteer/Kconfig')
-rw-r--r--src/mainboard/google/volteer/Kconfig5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig
index 73fe6c7142..3425a1981c 100644
--- a/src/mainboard/google/volteer/Kconfig
+++ b/src/mainboard/google/volteer/Kconfig
@@ -106,8 +106,7 @@ config MAINBOARD_PART_NUMBER
default "Volet" if BOARD_GOOGLE_VOLET
default "Chronicler" if BOARD_GOOGLE_CHRONICLER
-config PCIEXP_HOTPLUG
- default y
+if PCIEXP_HOTPLUG
# Reserving resources for PCIe Hotplug as per TGL BIOS Spec (doc #611569)
# Revision 0.7.6 Section 7.2.5.1.5
@@ -123,6 +122,8 @@ config PCIEXP_HOTPLUG_PREFETCH_MEM
hex
default 0x1c000000 # 448 MiB
+endif # PCIEXP_HOTPLUG
+
config TPM_TIS_ACPI_INTERRUPT
int
default 21 # GPE0_DW0_21 (GPP_C21)