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authorPatrick Georgi <pgeorgi@chromium.org>2015-12-12 00:23:15 +0100
committerPatrick Georgi <pgeorgi@google.com>2016-01-21 19:40:57 +0100
commit5d7ab39024705d872221aab126b42e743674d672 (patch)
tree54591e9c78ecfaf380a750926e3632c4c4cd2452 /src/mainboard/google/veyron_speedy
parente02be0e14ab0d53fbe270556e1a7752558014b36 (diff)
chromeos: import Chrome OS fmaps
These are generated from depthcharge's board/*/fmap.dts using the dts-to-fmd.sh script. One special case is google/veyron's chromeos.fmd, which is used for a larger set of boards - no problem since the converted fmd was the same for all of them. Set aside 128K for the bootblock on non-x86 systems (where the COREBOOT region ends up at the beginning of flash). This becomes necessary because we're working without a real cbfs master header (exists for transition only), which carved out the space for the offset. Change-Id: Ieeb33702d3e58e07e958523533f83da97237ecf1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12715 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/veyron_speedy')
-rw-r--r--src/mainboard/google/veyron_speedy/chromeos.fmd28
1 files changed, 28 insertions, 0 deletions
diff --git a/src/mainboard/google/veyron_speedy/chromeos.fmd b/src/mainboard/google/veyron_speedy/chromeos.fmd
new file mode 100644
index 0000000000..93afe34108
--- /dev/null
+++ b/src/mainboard/google/veyron_speedy/chromeos.fmd
@@ -0,0 +1,28 @@
+FLASH@0x0 0x400000 {
+ WP_RO@0x0 0x200000 {
+ RO_SECTION@0x0 0x1f0000 {
+ BOOTBLOCK@0 128K
+ COREBOOT(CBFS)@0x20000 0xe0000
+ FMAP@0x100000 0x1000
+ GBB@0x101000 0xeef00
+ RO_FRID@0x1eff00 0x100
+ }
+ RO_VPD@0x1f0000 0x10000
+ }
+ RW_SECTION_A@0x200000 0x78000 {
+ VBLOCK_A@0x0 0x2000
+ FW_MAIN_A(CBFS)@0x2000 0x75f00
+ RW_FWID_A@0x77f00 0x100
+ }
+ RW_SHARED@0x278000 0x4000 {
+ SHARED_DATA@0x0 0x4000
+ }
+ RW_ELOG@0x27c000 0x4000
+ RW_SECTION_B@0x280000 0x78000 {
+ VBLOCK_B@0x0 0x2000
+ FW_MAIN_B(CBFS)@0x2000 0x75f00
+ RW_FWID_B@0x77f00 0x100
+ }
+ RW_VPD@0x2f8000 0x8000
+ RW_LEGACY@0x300000 0x100000
+}