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authorChia-Ling Hou <chia-ling.hou@intel.com>2023-06-15 16:40:18 +0800
committerEric Lai <eric_lai@quanta.corp-partner.google.com>2023-08-10 07:31:22 +0000
commitdd1b0ec06e7af8e8cd2423ad7031979017ff04ad (patch)
treec3c7166a8c87b45d01f2afde2d87d0d30123239c /src/mainboard/google/veyron_rialto
parentbd054832d29e81a003c6ecf9e9d1bc5a6c9d845c (diff)
soc/intel/jasperlake: Add configs for USB 3.1 Gen2 EV settings
Add configs for USB 3.1 Gen2 electrical validation (EV) settings so that people can set the EV settings per board in device tree. BUG=b:285811345 TEST=build coreboot and fsp with enabled fw_debug. Flashed to taranza and checked the log. All usb configs were set correctly. Change-Id: Iecd12d3db76b63ad99887dee5991d94d47f138fd Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76246 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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