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| author | Wisley Chen <wisley.chen@quantatw.com> | 2016-11-15 03:51:13 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-11-17 18:48:49 +0100 |
| commit | 676b4878971b2fd782fbf97095d7cf0867ba00fe (patch) | |
| tree | 2f614c118889a20e2f8159d78d785d7f07e7e465 /src/mainboard/google/veyron_rialto | |
| parent | 9f2a411042c11d89d8e0a9c5459f5a250a505486 (diff) | |
google/snappy: Update DPTF settings
1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points.
CPU passive point:100, critical point:105
TSR1 passive point:48, critial point:65
TSR2 passive point:85, critial point:100
2. Update PL1/PL2 Min Power Limit/Max Power Limit
Set PL1 min to 3W, and max to 6W
Set PL2 min and max to 8W
3. Change thermal relationship table (TRT) setting.
The TRT of TCHG is TSR1, but real sensor is TSR2.
BRANCH=master
BUG=none
TEST= Compiled, verified by thermal team.
Change-Id: Ib197c36eca88e3d05f632025cf3c238e1a2eae23
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17426
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/google/veyron_rialto')
0 files changed, 0 insertions, 0 deletions