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| author | Bora Guvendik <bora.guvendik@intel.com> | 2017-10-13 15:15:48 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-17 22:49:43 +0000 |
| commit | 530c6f9cc8dd2c0cd0c586d3d14f11cb8021242f (patch) | |
| tree | b89237270f18e4c66b93061f223b03317579e6f9 /src/mainboard/google/veyron_rialto | |
| parent | de897a6dba1bc6ce157aed8c00cc20642c5d6c59 (diff) | |
intel/cannonlake_rvp: enable HS400
Set SCS emmc HS400 enable FSP parameter.
TEST=Boot to OS, verify HS400 SDHCI print
Change-Id: I3ef8a6740ef985a0c51115d9b0ea753b5db2c70d
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22008
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Diffstat (limited to 'src/mainboard/google/veyron_rialto')
0 files changed, 0 insertions, 0 deletions