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authorhuang lin <hl@rock-chips.com>2015-01-26 21:04:55 +0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-17 09:26:09 +0200
commitee28c86ccde1427e5f9aa4a110ee7d7f2629bc3c (patch)
tree3790ce6abda86308631a138d73dd937dd8d7e5f7 /src/mainboard/google/veyron_rialto/romstage.c
parentd37bc75632867e547ad4c8b1f333a1b5247c88e5 (diff)
rk3288: detect sdram size at runtime
we use Kconfig define sdram size before, but there may use different sdram size in the same overlay, so we must detect sdram size at runtime now. If we use 4G byte sdram, we can use[0x00000000:0xff000000], since the [0xff000000:0xffffffff] is the register space. BUG=chrome-os-partner:35521 TEST=Boot from mighty BRANCH=None Change-Id: I7a167c268483743c3eaed8b71c7ec545a688270c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ad4f27dd08c467888eee87e3d9c4ab3077751898 Original-Change-Id: Ib32aed50c9cae6db495ff3bab28266de91f3e73b Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/243139 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9734 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/veyron_rialto/romstage.c')
-rw-r--r--src/mainboard/google/veyron_rialto/romstage.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c
index c18471abe5..f3883bd28f 100644
--- a/src/mainboard/google/veyron_rialto/romstage.c
+++ b/src/mainboard/google/veyron_rialto/romstage.c
@@ -113,7 +113,7 @@ void main(void)
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
mmu_config_range((uintptr_t)_dram/MiB,
- CONFIG_DRAM_SIZE_MB, DCACHE_WRITEBACK);
+ sdram_size_mb(), DCACHE_WRITEBACK);
mmu_config_range((uintptr_t)_dma_coherent/MiB,
_dma_coherent_size/MiB, DCACHE_OFF);