diff options
author | Julius Werner <jwerner@chromium.org> | 2015-01-21 17:39:49 -0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-17 09:56:49 +0200 |
commit | 105f5b737bf8de88e37ed991d7469e84cef17c45 (patch) | |
tree | 4b089579ba460e8bcaea9f85085f50491a2100df /src/mainboard/google/veyron_jerry | |
parent | a5d2a8d18be1bfb1a7787c2e845a38404e422151 (diff) |
chromeos: Provide common watchdog reboot support
Many ChromeOS devices use a GPIO to reset the system, in order to
guarantee that the TPM cannot be reset without also resetting the CPU.
Often chipset/SoC hardware watchdogs trigger some kind of built-in
CPU reset, bypassing this GPIO and thus leaving the TPM locked. These
ChromeOS devices need to detect that condition in their bootblock and
trigger a second (proper) reboot.
This patch adds some code to generalize this previously
mainboard-specific functionality and uses it on Veyron boards. It also
provides some code to add the proper eventlog entry for a watchdog
reset. Since the second reboot has to happen before firmware
verification and the eventlog is usually only initialized afterwards, we
provide the functionality to place a tombstone in a memlayout-defined
location (which could be SRAM or some MMIO register that is preserved
across reboots).
[pg: Integrates
'mips: Temporarily work around build error caused by <arch/io.h> mismatch]
BRANCH=veyron
BUG=chrome-os-partner:35705
TEST=Run 'mem w 0xff800000 0x9' on a Jerry, watch how a "Hardware
watchdog reset" event appears in the eventlog after the reboot.
Change-Id: I0a33820b236c9328b2f9b20905b69cb934326f2a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fffc484bb89f5129d62739dcb44d08d7f5b30b33
Original-Change-Id: I7ee1d02676e9159794d29e033d71c09fdf4620fd
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/242404
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Id: c919c72ddc9d2e1e18858c0bf49c0ce79f2bc506
Original-Change-Id: I509c842d3393bd810e89ebdf0dc745275c120c1d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/242504
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9749
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/google/veyron_jerry')
-rw-r--r-- | src/mainboard/google/veyron_jerry/bootblock.c | 6 | ||||
-rw-r--r-- | src/mainboard/google/veyron_jerry/mainboard.c | 1 |
2 files changed, 3 insertions, 4 deletions
diff --git a/src/mainboard/google/veyron_jerry/bootblock.c b/src/mainboard/google/veyron_jerry/bootblock.c index 90ad744980..acf81bc0cb 100644 --- a/src/mainboard/google/veyron_jerry/bootblock.c +++ b/src/mainboard/google/veyron_jerry/bootblock.c @@ -58,10 +58,8 @@ void bootblock_mainboard_init(void) udelay(100);/* Must wait for voltage to stabilize,2mV/us */ rkclk_configure_cpu(); - if (rkclk_was_watchdog_reset()) { - printk(BIOS_INFO, "Last reset was watchdog... rebooting via GPIO!\n"); - hard_reset(); - } + if (rkclk_was_watchdog_reset()) + reboot_from_watchdog(); /* i2c1 for tpm */ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); diff --git a/src/mainboard/google/veyron_jerry/mainboard.c b/src/mainboard/google/veyron_jerry/mainboard.c index 00060a7679..1fc823c5fe 100644 --- a/src/mainboard/google/veyron_jerry/mainboard.c +++ b/src/mainboard/google/veyron_jerry/mainboard.c @@ -123,6 +123,7 @@ static void mainboard_init(device_t dev) configure_vop(); elog_init(); + elog_add_watchdog_reset(); elog_add_boot_reason(); } |