veyron_*: Remove obsolete Chromeboxes

This removes brain, danger, emile, and romy from the tree.

This was cherry-picked from the chromeos-2016.02 branch (CL:345574),
but conflicts showed up in many files that were to be deleted anyway
possibly due to some widespread refactoring that was done between
then and now.

BUG=chromium:612660
BRANCH=none
TEST=none

Change-Id: Ie37140a9a4bb9d820a3fcbad6674b2fa737e1249
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1ebe5038a82162f6345e319de7578f26ccd68b73
Original-Change-Id: I11f7e0870916871d8f146a6871370ace76ddec49
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/412424
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17569
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>

1 files changed, 0 insertions, 103 deletions

diff --git a/src/mainboard/google/veyron_brain/romstage.c b/src/mainboard/google/veyron_brain/romstage.c
deleted file mode 100644
index 1c139f1c2b..0000000000
--- a/src/mainboard/google/veyron_brain/romstage.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Rockchip Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/stages.h>
-#include <armv7.h>
-#include <assert.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <soc/sdram.h>
-#include <soc/clock.h>
-#include <soc/pwm.h>
-#include <soc/grf.h>
-#include <soc/rk808.h>
-#include <soc/tsadc.h>
-#include <stdlib.h>
-#include <symbols.h>
-#include <timestamp.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-#include "board.h"
-
-static void regulate_vdd_log(unsigned int mv)
-{
-	unsigned int duty_ns;
-	const u32 period_ns = 2000;	/* pwm period: 2000ns */
-	const u32 max_regulator_mv = 1350;	/* 1.35V */
-	const u32 min_regulator_mv = 870;	/* 0.87V */
-
-	write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
-
-	assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
-
-	duty_ns = (max_regulator_mv - mv) * period_ns /
-			(max_regulator_mv - min_regulator_mv);
-
-	pwm_init(1, period_ns, duty_ns);
-}
-
-static void configure_l2ctlr(void)
-{
-	uint32_t l2ctlr;
-
-	l2ctlr = read_l2ctlr();
-	l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
-	/*
-	* Data RAM write latency: 2 cycles
-	* Data RAM read latency: 2 cycles
-	* Data RAM setup latency: 1 cycle
-	* Tag RAM write latency: 1 cycle
-	* Tag RAM read latency: 1 cycle
-	* Tag RAM setup latency: 1 cycle
-	*/
-	l2ctlr |= (1 << 3 | 1 << 0);
-	write_l2ctlr(l2ctlr);
-}
-
-void main(void)
-{
-	timestamp_add_now(TS_START_ROMSTAGE);
-
-	console_init();
-	exception_init();
-	configure_l2ctlr();
-	tsadc_init();
-
-	/* vdd_log 1200mv is enough for ddr run 666Mhz */
-	regulate_vdd_log(1200);
-
-	timestamp_add_now(TS_BEFORE_INITRAM);
-
-	sdram_init(get_sdram_config());
-
-	timestamp_add_now(TS_AFTER_INITRAM);
-
-	/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
-	mmu_config_range((uintptr_t)_dram/MiB,
-			 sdram_size_mb(), DCACHE_WRITEBACK);
-	mmu_config_range((uintptr_t)_dma_coherent/MiB,
-			 _dma_coherent_size/MiB, DCACHE_OFF);
-
-	cbmem_initialize_empty();
-
-	run_ramstage();
-}