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authorJulius Werner <jwerner@chromium.org>2019-03-05 16:53:33 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-03-08 08:33:24 +0000
commitcd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch)
tree8e89136e2da7cf54453ba8c112eda94415b56242 /src/mainboard/google/veyron
parentb3a8cc54dbaf833c590a56f912209a5632b71f49 (diff)
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/google/veyron')
-rw-r--r--src/mainboard/google/veyron/boardid.c2
-rw-r--r--src/mainboard/google/veyron/bootblock.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/veyron/boardid.c b/src/mainboard/google/veyron/boardid.c
index 604b399676..c9c68ccd5b 100644
--- a/src/mainboard/google/veyron/boardid.c
+++ b/src/mainboard/google/veyron/boardid.c
@@ -38,7 +38,7 @@ uint32_t ram_code(void)
gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
[1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
- if (IS_ENABLED(CONFIG_VEYRON_FORCE_BINARY_RAM_CODE))
+ if (CONFIG(VEYRON_FORCE_BINARY_RAM_CODE))
code = gpio_base2_value(pins, ARRAY_SIZE(pins));
else
code = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins));
diff --git a/src/mainboard/google/veyron/bootblock.c b/src/mainboard/google/veyron/bootblock.c
index 4c2f1439b6..86834bfd71 100644
--- a/src/mainboard/google/veyron/bootblock.c
+++ b/src/mainboard/google/veyron/bootblock.c
@@ -31,7 +31,7 @@
void bootblock_mainboard_early_init()
{
- if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) {
+ if (CONFIG(CONSOLE_SERIAL)) {
assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
}