coreboot: rk3288: Add a stub implementation of the rk3288 SOC

Most things still needs to be filled in, but this will allow us to build boards which use this SOC.

BUG=chrome-os-partner:29778
TEST=emerge-veyron coreboot

Original-Change-Id: If643d620c5fb8951faaf1ccde400a8e9ed7db3bc
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205069
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 2f72473a8c2b3fe21d77b351338e6209035878fb)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I53fd0ced42f6ef191d7bf80d8b823bb880344239
Reviewed-on: http://review.coreboot.org/8653
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 59 insertions, 0 deletions

diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c
new file mode 100644
index 0000000000..b9daefe6b9
--- /dev/null
+++ b/src/mainboard/google/veyron/romstage.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <armv7.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <arch/stages.h>
+#include <cbmem.h>
+#include <delay.h>
+#include <timestamp.h>
+#include <arch/cache.h>
+#include <arch/exception.h>
+
+void main(void)
+{
+	void *entry;
+
+	console_init();
+
+	/* used for MMU and CBMEM setup, in MB */
+	u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
+	u32 dram_size = CONFIG_DRAM_SIZE_MB;
+	u32 dram_end = dram_start + dram_size;
+	mmu_init();
+	/* Device memory below DRAM is uncached. */
+	mmu_config_range(0, dram_start, DCACHE_OFF);
+	/* DRAM is cached. */
+	mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
+	/* A window for DMA is uncached. */
+	mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
+			 CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
+	/* The space above DRAM is uncached. */
+	if (dram_end < 4096)
+		mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
+	mmu_disable_range(0, 1);
+	dcache_mmu_enable();
+
+	cbmem_initialize_empty();
+
+	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
+	stage_exit(entry);
+}