diff options
| author | Kane Chen <kane.chen@intel.com> | 2017-10-11 12:39:46 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-10-16 00:20:07 +0000 |
| commit | 6708d3abc744d3d51472ef0028f9a7ad96fd8f11 (patch) | |
| tree | 7b5ea32e2477bdd9ae4bbc30d6085804eb1dca5b /src/mainboard/google/veyron/chromeos.c | |
| parent | ec1a24ca02221daeef521ccc8d934a7e0abb7ae5 (diff) | |
mb/google/fizz: enable AER for PCIe root ports
Enable PCIe Advanced Error Reporting for PCIe
root port 2, 3, 4 ,8.
BUG=b:64798078
TEST="lspci" shows that AER is enabled in the capabilities list.
Change-Id: I6438250d674e7d06cdecd8f25fadebca1973721e
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/21946
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/google/veyron/chromeos.c')
0 files changed, 0 insertions, 0 deletions