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authorJulius Werner <jwerner@chromium.org>2020-02-06 16:44:40 -0800
committerJulius Werner <jwerner@chromium.org>2020-05-12 00:01:21 +0000
commit561b8cc2e7469af7ad0796304a0c51684551e59a (patch)
treeddc964d22b22989b11f7789757bea1f27b78df2d /src/mainboard/google/trogdor/bootblock.c
parent8ad0c86da28debba1cd65b1d1fc898697220581c (diff)
trogdor: Add support for rev1
This patch implements the pin changes needed for Trogdor rev1. Unfortunately, coreboot has to get the EC and TPM SPI busses compiled into Kconfig, so we cannot really build a single image that runs on both revisions. Introduce a Kconfig to handle this instead. Change-Id: I2e48dc4565682c12089b6cf92c29f4cef4d61bb8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/trogdor/bootblock.c')
-rw-r--r--src/mainboard/google/trogdor/bootblock.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/mainboard/google/trogdor/bootblock.c b/src/mainboard/google/trogdor/bootblock.c
index b17c2e7d91..710a2e7734 100644
--- a/src/mainboard/google/trogdor/bootblock.c
+++ b/src/mainboard/google/trogdor/bootblock.c
@@ -2,12 +2,11 @@
#include <bootblock_common.h>
#include "board.h"
-#include <soc/qcom_qup_se.h>
#include <soc/qupv3_spi.h>
void bootblock_mainboard_init(void)
{
setup_chromeos_gpios();
- qup_spi_init(QUPV3_1_SE0, 1010 * KHz); /* H1 SPI */
- qup_spi_init(QUPV3_0_SE0, 1010 * KHz); /* EC SPI */
+ qup_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, 1010 * KHz);
+ qup_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 1010 * KHz);
}