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authorArthur Heymans <arthur@aheymans.xyz>2019-01-21 17:55:02 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-01-24 13:39:19 +0000
commit7e6946a74c714ff109c35d97001b22c9e868aaea (patch)
tree98899e89dc00f8e5504f06d84eb6dc44227b4c80 /src/mainboard/google/stout
parentd6c15d0c8c39015994a180da82c3e6f9538b42de (diff)
cpu/intel/model_206ax: Remove the notion of sockets
With the memory controller the separate sockets becomes a useless distinction. They all used the same code anyway. UNTESTED: This also updates autoport. Change-Id: I044d434a5b8fca75db9eb193c7ffc60f3c78212b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/31031 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/stout')
-rw-r--r--src/mainboard/google/stout/Kconfig1
-rw-r--r--src/mainboard/google/stout/devicetree.cb4
2 files changed, 1 insertions, 4 deletions
diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig
index bfd45ea600..c9b67ccee1 100644
--- a/src/mainboard/google/stout/Kconfig
+++ b/src/mainboard/google/stout/Kconfig
@@ -3,7 +3,6 @@ if BOARD_GOOGLE_STOUT
config BOARD_SPECIFIC_OPTIONS
def_bool y
select SYSTEM_TYPE_LAPTOP
- select CPU_INTEL_SOCKET_RPGA989
select NORTHBRIDGE_INTEL_IVYBRIDGE
select SOUTHBRIDGE_INTEL_C216
select EC_QUANTA_IT8518
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
index 31407820a1..ddcf4e22d1 100644
--- a/src/mainboard/google/stout/devicetree.cb
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -23,11 +23,9 @@ chip northbridge/intel/sandybridge
register "max_mem_clock_mhz" = "666"
device cpu_cluster 0 on
- chip cpu/intel/socket_rPGA989
- device lapic 0 on end
- end
chip cpu/intel/model_206ax
# Magic APIC ID to locate this chip
+ device lapic 0x0 on end
device lapic 0xacac off end
register "tcc_offset" = "5" # TCC of 95C