diff options
| author | Nick Vaccaro <nvaccaro@google.com> | 2020-01-28 00:31:26 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-09 19:26:36 +0000 |
| commit | b1fa25fab7af09fa90a7a83f283e51358069d333 (patch) | |
| tree | 113bdd2a752324cac24e758c15cc4321b1efd610 /src/mainboard/google/stout | |
| parent | f978191b64bf0b4a512eb2872e044f1e030b7c8f (diff) | |
soc/intel/tigerlake: add memory configuration support
Move some of the common memory code that was being performed in
mainboard into the soc to reduce redundant code going forward.
BUG=b:145642089
BRANCH=none
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
volteer, log into kernel and verify memory size shows 8GB.
Change-Id: I8de502d4f05d52b9dae34e3b013c6d5b1886fa55
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/stout')
0 files changed, 0 insertions, 0 deletions