diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-06-04 13:00:36 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-06-07 11:37:17 +0000 |
| commit | 427e435b9ba28ebc9f5ee5535ba06c73e07f40c8 (patch) | |
| tree | 4b2031d367d8c0c71dce500bfa9bb427a1419d0b /src/mainboard/google/stout/devicetree.cb | |
| parent | 685dc56b9f2cf639c8aa72eed948e02044683642 (diff) | |
sb/intel/bd82x6x: Drop P_LVLx support in FADT
IO MWAIT redirection is not enabled, and C-states are reported using the
_CST ACPI object, which overrides the P_LVLx values.
Change-Id: I737bd58bcda3e7c5f6591e4c2309530ff035e2c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/google/stout/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/stout/devicetree.cb | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 914ab601e0..ad700cee29 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -63,8 +63,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "1" - device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 |