diff options
| author | Keith Hui <buurin@gmail.com> | 2024-02-05 19:18:43 -0500 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2024-06-08 00:19:23 +0000 |
| commit | a911b758482025d46e132eeb2ed0279b65692075 (patch) | |
| tree | fb8475ef03a0365132fefb82bc248468ef0a4784 /src/mainboard/google/stout/devicetree.cb | |
| parent | ee126348726b24fbf6e5435bb2cf15417959a8f7 (diff) | |
mb/*: Remove old USB configurations from SNB/bd82x6x boards
Remove USB configurations and data structures from northbridge
devicetree (SNB+MRC boards) and bootblock/romstage C code
(native-only SNB boards). All USB configurations are drawn from
southbridge devicetree going forward.
Change-Id: Ie1cd21077136998a6e90050c95263f2efed68a67
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81882
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/stout/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/stout/devicetree.cb | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 36e8ba79f6..0211921c38 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -22,22 +22,6 @@ chip northbridge/intel/sandybridge # FIXME: Native raminit requires reduced max clock register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800" - register "usb_port_config" = "{ - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 0, 1, 0x0000 }, - { 1, 1, 0x0040 }, - { 1, 1, 0x0040 }, - { 1, 1, 0x0040 }, - { 0, 1, 0x0000 }, - { 0, 1, 0x0000 }, - { 0, 5, 0x0000 }, - { 1, 4, 0x0040 }, - { 0, 5, 0x0000 }, - { 0, 5, 0x0000 }, - { 0, 5, 0x0000 }, - { 1, 5, 0x0040 },}" - register "usb3.mode" = "2" # Auto register "usb3.hs_port_switch_mask" = "3" # Ports 0 & 1 register "usb3.preboot_support" = "0" # No PreOS boot support |