diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2013-06-19 15:54:19 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2013-12-21 18:30:47 +0100 |
| commit | 662874446a55356ed74ebf7acdcfa276752214bf (patch) | |
| tree | e8ffb7966fb0d1ff045c4543bb8265027dd1c740 /src/mainboard/google/snow | |
| parent | d9a98581ce5f94b2c8278aafcbb845f630ad7d71 (diff) | |
Exynos 5250: Enable dynamic CBMEM
... In order to do this, the graphics memory has to move into
the resource allocator and out of CBMEM.
Change-Id: I7396da4a7068404b0d2e4d308becab4dd6ea59bb
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/59326
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4390
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/google/snow')
| -rw-r--r-- | src/mainboard/google/snow/mainboard.c | 7 | ||||
| -rw-r--r-- | src/mainboard/google/snow/romstage.c | 3 |
2 files changed, 8 insertions, 2 deletions
diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c index 0d194b45dc..4d7d43c45f 100644 --- a/src/mainboard/google/snow/mainboard.c +++ b/src/mainboard/google/snow/mainboard.c @@ -213,7 +213,7 @@ static void mainboard_init(device_t dev) .base = (struct exynos5_dp *)EXYNOS5250_DP1_BASE, .video_info = &dp_video_info, }; - void *fb_addr; + void *fb_addr = (void *)(get_fb_base_kb() * KiB); gpio_init(); @@ -228,7 +228,6 @@ static void mainboard_init(device_t dev) /* Disable USB3.0 PLL to save 250mW of power */ disable_usb30_pll(); - fb_addr = cbmem_find(CBMEM_ID_CONSOLE); set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); lcd_vdd(); @@ -265,6 +264,7 @@ static void mainboard_init(device_t dev) // gpio_info(); } +#if !CONFIG_DYNAMIC_CBMEM void get_cbmem_table(uint64_t *base, uint64_t *size) { *size = CONFIG_COREBOOT_TABLES_SIZE; @@ -272,13 +272,16 @@ void get_cbmem_table(uint64_t *base, uint64_t *size) ((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) - CONFIG_COREBOOT_TABLES_SIZE; } +#endif static void mainboard_enable(device_t dev) { dev->ops->init = &mainboard_init; +#if !CONFIG_DYNAMIC_CBMEM /* set up coreboot tables */ cbmem_initialize(); +#endif /* set up dcache and MMU */ /* FIXME: this should happen via resource allocator */ diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 7442f7afc2..f69fb1f7eb 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -21,6 +21,7 @@ #include <armv7.h> #include <cbfs.h> +#include <cbmem.h> #include <arch/cache.h> #include <cpu/samsung/exynos5250/i2c.h> @@ -189,6 +190,8 @@ void main(void) /* Set SPI (primary CBFS media) clock to 50MHz. */ clock_set_rate(PERIPH_ID_SPI1, 50000000); + cbmem_initialize_empty(); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); stage_exit(entry); } |